RESUMEN
Two-dimensional (2D) van der Waals (vdW) multiferroic tunnel junctions (MFTJs) composed of a ferromagnetic metal and a ferroelectric barrier have controllable thickness and clean interface and can realize the coexistence of tunneling magnetoresistance (TMR) and tunneling electroresistance (TER). Therefore, they have enormous potential application in nonvolatile multistate memories. Here, using first principles combined with non-equilibrium Green's function method, we have systematically investigated the spin-dependent transport properties of Fe3GeTe2/MnSe/Fe3GeTe2 vdW MFTJs with various numbers of barrier layers. By controlling the polarization orientation of the ferroelectric barrier MnSe and the magnetization alignment of the ferromagnetic electrodes Fe3GeTe2, the MnSe-based MFTJs exhibit four nonvolatile resistance states, with the TMR (TER) becoming higher and reaching a maximum of 1.4 × 106% (4114%) as the MnSe layers increase from a bilayer to a tetralayer. Using asymmetric Cu and Fe3GeTe2 as the electrodes, the TER can be further improved from 349% to 618%. Moreover, there is a perfect spin filtering effect in these MFTJs. This work demonstrates the potential applications of MnSe-based devices in multistate nonvolatile memories and spin filters, which will stimulate experimental studies on layer-controllable spintronic devices.
RESUMEN
Due to the ability to reduce the gate length of field-effect transistors (FETs) down to sub-10 nm without obviously affecting the performance of the device, the utilization of two-dimensional (2D) semiconductor materials as channel materials for FETs is of great interest. However, in-plane 2D/2D heterojunction FETs have received less attention in previous studies than vertical van der Waals heterojunction devices. Based on the above reasons, this study has investigated the transport properties of an in-plane NbSe2/MoSe2/NbSe2 heterojunction FET with different gate lengths by using ab initio quantum transport simulation. The results reveal that a gate length of sub-9 nm gives the device a low subthreshold swing down to 62 mV dec-1 and a high on-state current up to 1040 µA µm-1. Most importantly, the on-state current, delay time, and power dissipation of the FET with the optimized channel length can nearly meet or even exceed the high-performance and low-power requirements of the International Technology Roadmap for Semiconductors. The findings for this FET can provide the design and development guidance for other in-plane heterojunction electrical devices in the post-Moore era.