RESUMEN
This article introduces a novel method for designing a fast chaotic oscillator using a CCTA (Current Conveyor Transconductance Amplifier) based on Chua's circuit. The proposed method uses innovative configurations and advanced simulation techniques to overcome challenges in high-speed operation, nonlinear dynamics, and Analog Building Block (ABB) selection. The design begins with nonlinear negative resistance, essential for Chua's diode characteristics, including two negative resistances, NR1 and NR2. The circuit integrates one CCTA block, two grounded capacitors, two fixed resistors, one inductor, and one potentiometer. It is simulated using PSPICE with IC (Integrated Circuit) macro-models and 180nm CMOS (Complementary Metal Oxide Semiconductor) technology. Various chaotic waveforms and attractors are produced, validating the theoretical and mathematical predictions. By varying the resistance values (1450Ω, 1650Ω, 1800Ω, 1950Ω), the circuit exhibits different chaotic behaviors, such as large limit cycles, double-scroll attractors, Rossler-type attractors, and I-periodic attractors. FFT (Fast Fourier Transform) analysis confirms the highest dominant operating frequency of 37.5MHz. A Monte Carlo simulation with 100 runs shows maximum voltage variations in the chaotic waveforms of 5.21 % and 4.61 % across the capacitors, demonstrating robustness and reliability. This design offers significant advancements in implementing high-frequency chaotic oscillators, with potential applications in various fields requiring chaotic signal generation.â¢A novel design of Chua's diode and Chua's chaotic oscillator using only one CCTA block is presented in this paper.â¢The proposed chaotic oscillator achieves the highest operating frequency of 37.5MHz.â¢The proposed circuit is simulated using commercially available ICs (MAX435 and AD844) and CMOS 180nm technology in PSPICE to confirm its workability.
RESUMEN
A compact 1 × 4 antipodal Vivaldi antenna (AVA) array designed for 5 G applications is introduced in this study. An elliptical-shaped parasitic patch and corrugation are strategically employed to enhance gain and bandwidth, making it well-suited for 5 G applications. The resulting AVA array with corrugation and parasitic patch (AVA-PC) is designed and simulated on ANSYS HFSS, demonstrating a stable gain ranging from 10 dBi to 11.7 dBi over the frequency range of 23.45 GHz to 28.74 GHz. The antenna, with 25.8 mm x 22.4 mm x 0.5 mm dimensions, is implemented on Roger's RT/Duroid substrate 5880. â¢Design uses an antipodal Vivaldi antenna to build a 1 × 4 AVA.â¢The array employs corrugations and an elliptical patch as a performance enhancement technique.â¢Simulated results confirm the designed antenna's practical utility for 5 G applications in a band of 23.45 GHz to 28.74 GHz.
RESUMEN
An analog comb filter is implemented by linking multiple VDCC-based notch filters in a cascading fashion (N in total), eliminating N different pole frequencies. This study focuses on suppressing a fundamental frequency of power-line interference of 50 Hz and its consecutive three odd harmonics at 150 Hz, 250 Hz, and 350 Hz. One significant advantage of this comb filter is the independent control over filters' parameters like quality factor and pole frequency. Additionally, these filters can be electronically tuned by adjusting the transconductance gain of VDCC. The suggested notch filter configuration involves 2 capacitors, 2 resistors, and 1 VDCC element. Extensive simulations were conducted using PSPICE simulator software to validate the effectiveness of these filters. The basic building block, VDCC, is designed and implemented in the simulation using integrated circuits MAX435 and AD844.â¢Design uses a VDCC-based high Q notch filter as the active building block.â¢The filter employs fewer active and passive components.â¢Simulated results using commercially available ICs, MAX435 and AD844, confirm the filter's practical utility.