Robust Chemiresistive Behavior in Conductive Polymer/MOF Composites.

Metal-organic frameworks (MOFs) are promising materials for gas sensing but are often limited to single-use detection. A hybridization strategy is demonstrated synergistically deploying conductive MOFs (cMOFs) and conductive polymers (cPs) as two complementary mixed ionic-electronic conductors in high-performing stand-alone chemiresistors. This work presents significant improvement in i) sensor recovery kinetics, ii) cycling stability, and iii) dynamic range at room temperature. The effect of hybridization across well-studied cMOFs is demonstrated based on 2,3,6,7,10,11-hexahydroxytriphenylene (HHTP) and 2,3,6,7,10,11-hexaiminotriphenylene (HITP) ligands with varied metal nodes (Co, Cu, Ni). A comprehensive mechanistic study is conducted to relate energy band alignments at the heterojunctions between the MOFs and the polymer with sensing thermodynamics and binding kinetics. The findings reveal that hole enrichment of the cMOF component upon hybridization leads to selective enhancement in desorption kinetics, enabling significantly improved sensor recovery at room temperature, and thus long-term response retention. This mechanism is further supported by density functional theory calculations on sorbate-analyte interactions. It is also found that alloying cPs and cMOFs enables facile thin film co-processing and device integration, potentially unlocking the use of these hybrid conductors in diverse electronic applications.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Nanosecond protonic programmable resistors for analog deep learning.

Nanoscale ionic programmable resistors for analog deep learning are 1000 times smaller than biological cells, but it is not yet clear how much faster they can be relative to neurons and synapses. Scaling analyses of ionic transport and charge-transfer reaction rates point to operation in the nonlinear regime, where extreme electric fields are present within the solid electrolyte and its interfaces. In this work, we generated silicon-compatible nanoscale protonic programmable resistors with highly desirable characteristics under extreme electric fields. This operation regime enabled controlled shuttling and intercalation of protons in nanoseconds at room temperature in an energy-efficient manner. The devices showed symmetric, linear, and reversible modulation characteristics with many conductance states covering a 20× dynamic range. Thus, the space-time-energy performance of the all-solid-state artificial synapses can greatly exceed that of their biological counterparts.

Neural Network Training With Asymmetric Crosspoint Elements.

Analog crossbar arrays comprising programmable non-volatile resistors are under intense investigation for acceleration of deep neural network training. However, the ubiquitous asymmetric conductance modulation of practical resistive devices critically degrades the classification performance of networks trained with conventional algorithms. Here we first describe the fundamental reasons behind this incompatibility. Then, we explain the theoretical underpinnings of a novel fully-parallel training algorithm that is compatible with asymmetric crosspoint elements. By establishing a powerful analogy with classical mechanics, we explain how device asymmetry can be exploited as a useful feature for analog deep learning processors. Instead of conventionally tuning weights in the direction of the error function gradient, network parameters can be programmed to successfully minimize the total energy (Hamiltonian) of the system that incorporates the effects of device asymmetry. Our technique enables immediate realization of analog deep learning accelerators based on readily available device technologies.

CMOS-Compatible Protonic Programmable Resistor Based on Phosphosilicate Glass Electrolyte for Analog Deep Learning.

Ion intercalation based programmable resistors have emerged as a potential next-generation technology for analog deep-learning applications. Proton, being the smallest ion, is a very promising candidate to enable devices with high modulation speed, low energy consumption, and enhanced endurance. In this work, we report on the first back-end CMOS-compatible nonvolatile protonic programmable resistor enabled by the integration of phosphosilicate glass (PSG) as the proton solid electrolyte layer. PSG is an outstanding solid electrolyte material that displays both excellent protonic conduction and electronic insulation characteristics. Moreover, it is a well-known material within conventional Si fabrication, which enables precise deposition control and scalability. Our scaled all-solid-state three-terminal devices show desirable modulation characteristics in terms of symmetry, retention, endurance, and energy efficiency. Protonic programmable resistors based on phosphosilicate glass, therefore, represent promising candidates to realize nanoscale analog crossbar processors for monolithic CMOS integration.

Protonic solid-state electrochemical synapse for physical neural networks.

Physical neural networks made of analog resistive switching processors are promising platforms for analog computing. State-of-the-art resistive switches rely on either conductive filament formation or phase change. These processes suffer from poor reproducibility or high energy consumption, respectively. Herein, we demonstrate the behavior of an alternative synapse design that relies on a deterministic charge-controlled mechanism, modulated electrochemically in solid-state. The device operates by shuffling the smallest cation, the proton, in a three-terminal configuration. It has a channel of active material, WO3. A solid proton reservoir layer, PdHx, also serves as the gate terminal. A proton conducting solid electrolyte separates the channel and the reservoir. By protonation/deprotonation, we modulate the electronic conductivity of the channel over seven orders of magnitude, obtaining a continuum of resistance states. Proton intercalation increases the electronic conductivity of WO3 by increasing both the carrier density and mobility. This switching mechanism offers low energy dissipation, good reversibility, and high symmetry in programming.

In Situ Thermal Atomic Layer Etching for Sub-5 nm InGaAs Multigate MOSFETs.

Thermal atomic layer etching (ALE) was demonstrated on ternary III-V compound semiconductors. In particular, thermal ALE on InGaAs and InAlAs was achieved with sequential, self-limiting fluorination and ligand-exchange reactions using hydrogen fluoride (HF) as the fluorination reactant and dimethylaluminum chloride (DMAC) as the ligand-exchange reactant. Thermal ALE was investigated on planar surfaces and three-dimensional nanostructures. The measured radial etch rates on In0.53Ga0.47As and In0.52Al0.48As vertical nanowires (VNWs) at 300 °C were 0.24 and 0.62 Å/cycle, respectively. An optimized thermal ALE process did not increase the surface roughness after 200 cycles. The etching process also displayed selectivity and orientation dependence. This new thermal ALE process in combination with in situ atomic layer deposition (ALD) was used to fabricate InGaAs gate-all-around structures with minimum width down to 3 nm. The in situ ALE-ALD process produced a sharp vertical MOS interface. Finally, the merits of thermal ALE were demonstrated in the fabrication of n-channel InGaAs FinFETs with record ON-state and OFF-state transistor performance. On the basis of this transistor demonstration, thermal ALE shows great promise for high-volume device manufacturing.

Enhanced transport in transistor by tuning transition-metal oxide electronic states interfaced with diamond.

High electron affinity transition-metal oxides (TMOs) have gained a central role in two-dimensional (2D) electronics by enabling unprecedented surface charge doping efficiency in numerous exotic 2D solid-state semiconductors. Among them, diamond-based 2D electronics are entering a new era by using TMOs as surface acceptors instead of previous molecular-like unstable acceptors. Similarly, surface-doped diamond with TMOs has recently yielded record sheet hole concentrations (2 × 1014 cm-2) and launched the quest for its implementation in microelectronic devices. Regrettably, field-effect transistor operation based on this surface doping has been so far disappointing due to fundamental material obstacles such as (i) carrier scattering induced by nonhomogeneous morphology of TMO surface acceptor layer, (ii) stoichiometry changes caused by typical transistor fabrication process, and (iii) carrier transport loss due to electronic band energy misalignment. This work proposes and demonstrates a general strategy that synergistically surmounts these three barriers by developing an atomic layer deposition of a hydrogenated MoO3 layer as a novel efficient surface charge acceptor for transistors. It shows high surface uniformity, enhanced immunity to harsh fabrication conditions, and benefits from tunable electronic gap states for improving carrier transfer at interfaces. These breakthroughs permit crucial integration of TMO surface doping into transistor fabrication flows and allow outperforming electronic devices to be reached.

Nanometre-scale electronics with III-V compound semiconductors.

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.