Effect of silicide/silicon hetero-junction structure on thermal conductivity and Seebeck coefficient.

We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured. The laminated thermoelectric device shows suppression of heat flow from the hot to cold side. This is supported by the theory that the atomic mass difference between silicide and silicon creates a scattering center for phonons. The major impact of our work is that phonon transmission is suppressed at the interface between silicide and silicon without degrading electrical conductivity. The estimated thermal conductivity of the 3-layer laminated device is 126.2 +/- 3.7 W/m. K. Thus, by using the 3-layer laminated structure, thermal conductivity is reduced by around 16% compared to bulk silicon. However, the Seebeck coefficient of the thermoelectric device is degraded compared to that of bulk silicon. It is understood that electrical conductivity is improved by using silicide as a scattering center.

Seebeck coefficient characterization of highly doped n- and p-type silicon nanowires for thermoelectric device applications fabricated with top-down approach.

A silicon nanowire one-dimensional thermoelectric device is presented as a solution to enhance thermoelectric performance. A top-down process is adopted for the definition of 50 nm silicon nanowires (SiNWs) and the fabrication of the nano-structured thermoelectric devices on silicon on insulator (SOl) wafer. To measure the Seebeck coefficients of 50 nm width n- and p-type SiNWs, a thermoelectric test structure, containing SiNWs, micro-heaters and temperature sensors is fabricated. Doping concentration is 1.0 x 10(20) cm(-3) for both for n- and p-type SiNWs. To determine the temperature gradient, a temperature coefficient of resistance (TCR) analysis is done and the extracted TCR value is 1750-1800 PPM x K(-1). The measured Seebeck coefficients are -127.583 microV x K(-1) and 141.758 microV x K(-1) for n- and p-type SiNWs, respectively, at room temperature. Consequently, power factor values are 1.46 mW x m(-1) x K(-2) and 1.66 mW x m(-1) x K(-2) for n- and p-type SiNWs, respectively. Our results indicate that SiNWs based thermoelectric devices have a great potential for applications in future energy conversion systems.

Evaluation of Seebeck coefficients in n- and p-type silicon nanowires fabricated by complementary metal-oxide-semiconductor technology.

Silicon-based thermoelectric nanowires were fabricated by using complementary metal-oxide-semiconductor (CMOS) technology. 50 nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8 inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated. Moreover, for the elimination of electrical and thermal contact resistance issues, the SiNWs, heater and temperature sensors were fabricated monolithically using a CMOS process. For validation of the temperature measurement by an electrical method, scanning thermal microscopy analysis was carried out. The highest Seebeck coefficients were - 169.97 µV K(-1) and 152.82 µV K(-1) and the highest power factors were 2.77 mW m(-1) K(-2) and 0.65 mW m(-1) K(-2) for n- and p-type SiNWs, respectively, in the temperature range from 200 to 300 K. The larger power factor value for n-type SiNW was due to the higher electrical conductivity. The total Seebeck coefficient and total power factor for the n- and p-leg unit device were 157.66 µV K(-1) and 9.30 mW m(-1) K(-2) at 300 K, respectively.

Top-down processed silicon nanowires for thermoelectric applications.

50 nm wide n-type silicon nanowires have been manufactured by using a top-down process in order to investigate the thermoelectric properties of silicon nanowire. Nanowire test structures with platinum heaters and temperature sensors were fabricated. The extracted temperature coefficient of resistance (TCR) of the temperature sensors was 786.6 PPM/K. Also, the extracted Seebeck coefficient and power factor of the 50 nm wide phosphorus doped n-type silicon nanowires were -118 miroV/K and 2.16 mW x K(-2) x m(-1).

Electrical characterization of n/p-type nickel silicide/silicon junctions by Sb segregation.

In this paper, n/p-type nickel-silicided Schottky diodes were fabricated by incorporating antimony atoms near the nickel silicide/Si junction interface and the electrical characteristics were studied through measurements and simulations. The effective Schottky barrier height (SBH) for electron, extracted from the thermionic emission model, drastically decreased from 0.68 to less than 0.1 eV while that for hole slightly increased from 0.43 to 0.53 eV. In order to identify the current conduction mechanisms, the experimental current-temperature-voltage characteristics for the n-type diode were fitted based on various models for transport of charge carrier in Schottky diodes. As the result, the large change in effective SBH for electron is ascribed to trap-assisted tunneling rather than barrier height inhomogeneity.

The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process.

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 µV/K for p-leg and -94 µV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K(2) at room temperature.