RESUMEN
The current semiconductor technology road map for device scaling champions a 4.5 nm gate length in production by 2022. The scanning electron microscope (SEM) as applied to critical dimensions (CD) metrology and associated characterization modes such as electron beam-induced current and cathodoluminescence (CL) has proved to be a workhorse for the semiconductor industry during the microelectronics era. We review some of the challenges facing these techniques in light of the silicon nanotechnology road map. We present some new results using voltage contrast imaging and CL spectroscopy of top-down fabricated silicon nanopillar/nanowires (<100 nm diameter), which highlight the visualization challenge. However, both techniques offer the promise of providing process characterization on the 10-20 nm scale with existing technology. Visualization at the 1 nm scale with these techniques may have to wait for aberration-corrected SEM to become more widely available. Basic secondary electron imaging and CD applications may be separately addressed by the He-ion microscope.