Mobility Extraction in 2D Transition Metal Dichalcogenide Devices-Avoiding Contact Resistance Implicated Overestimation.

Schottky barrier (SB) transistors operate distinctly different from conventional metal-oxide semiconductor field-effect transistors, in a unique way that the gate impacts the carrier injection from the metal source/drain contacts into the channel region. While it has been long recognized that this can have severe implications for device characteristics in the subthreshold region, impacts of contact gating of SB in the on-state of the devices, which affects evaluation of intrinsic channel properties, have been yet comprehensively studied. Due to the fact that contact resistance (RC ) is always gate-dependent in a typical back-gated device structure, the traditional approach of deriving field-effect mobility from the maximum transconductance (gm ) is in principle not correct and can even overestimate the mobility. In addition, an exhibition of two different threshold voltages for the channel and the contact region leads to another layer of complexity in determining the true carrier concentration calculated from Q = COX * (VG -VTH ). Through a detailed experimental analysis, the effect of different effective oxide thicknesses, distinct SB heights, and doping-induced reductions in the SB width are carefully evaluated to gain a better understanding of their impact on important device metrics.

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing.

In this paper, electrostatically configurable 2D tungsten diselenide (WSe2 ) electronic devices are demonstrated. Utilizing a novel triple-gate design, a WSe2 device is able to operate as a tunneling field-effect transistor (TFET), a metal-oxide-semiconductor field-effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band-to-band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self-consistent full-band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub-60 mV dec-1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low-power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.

Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2.

Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS2 FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.

Improvement in the breakdown endurance of high-κ dielectric by utilizing stacking technology and adding sufficient interfacial layer.

Improvement in the time-zero dielectric breakdown (TZDB) endurance of metal-oxide-semiconductor (MOS) capacitor with stacking structure of Al/HfO2/SiO2/Si is demonstrated in this work. The misalignment of the conduction paths between two stacking layers is believed to be effective to increase the breakdown field of the devices. Meanwhile, the resistance of the dielectric after breakdown for device with stacking structure would be less than that of without stacking structure due to a higher breakdown field and larger breakdown power. In addition, the role of interfacial layer (IL) in the control of the interface trap density (D it) and device reliability is also analyzed. Device with a thicker IL introduces a higher breakdown field and also a lower D it. High-resolution transmission electron microscopy (HRTEM) of the samples with different IL thicknesses is provided to confirm that IL is needed for good interfacial property.