RESUMEN
Preparing Cd3As2, which is a three-dimensional (3D) Dirac semimetal in certain crystal orientation, on Si is highly desirable as such a sample may well be fully compatible with existing Si CMOS technology. However, there is a dearth of such a study regarding Cd3As2films grown on Si showing the chiral anomaly. Here,for the first time, we report the novel preparation and fabrication technique of a Cd3As2(112) film on a Si (111) substrate with a ZnTe (111) buffer layer which explicitly shows the chiral anomaly with a nontrivial Berry's phase ofπ. Despite the Hall carrier density (n3D≈9.42×1017cm-3) of our Cd3As2film, which is almost beyond the limit for the portents of a 3D Dirac semimetal to emerge, we observe large linear magnetoresistance in a perpendicular magnetic field and negative magnetoresistance in a parallel magnetic field. These results clearly demonstrate the chiral magnetic effect and 3D Dirac semimetallic behavior in our silicon-based Cd3As2film. Our tailoring growth of Cd3As2on a conventional substrate such as Si keeps the sample quality, while also achieving a low carrier concentration.
RESUMEN
A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.
RESUMEN
The magnetotransport properties of a hybrid InSe/monolayer graphene in a SiC system are systematically studied. Compared to those of its bare graphene counterpart, in InSe/graphene, we can effectively modify the carrier density, mobility, effective mass, and electron-electron (e-e) interactions enhanced by weak disorder. We show that in bare graphene and hybrid InSe/graphene systems, the logarithmic temperature (lnT) dependence of the Hall slope R H = δR xy /δB = δρ xy /δB can be used to probe e-e interaction effects at various temperatures even when the measured resistivity does not show a lnT dependence due to strong electron-phonon scattering. Nevertheless, one needs to be certain that the change of R H is not caused by an increase of the carrier density by checking the magnetic field position of the longitudinal resistivity minimum at different temperatures. Given the current challenges in gating graphene on SiC with a suitable dielectric layer, our results suggest that capping a van der Waals material on graphene is an effective way to modify the electronic properties of monolayer graphene on SiC.
RESUMEN
Excited conduction electrons, conduction holes, and valence holes in monolayer electron-doped graphene exhibit unusual Coulomb decay rates. The deexcitation processes are studied using the screened exchange energy. They might utilize the intraband and interband single-particle excitations, as well as the plasmon modes, depending on the quasiparticle states and the Fermi energies. The low-lying valence holes can decay through the undamped acoustic plasmon, so that they present very fast Coulomb deexcitations, nonmonotonous energy dependence, and anisotropic behavior. However, the low-energy conduction electrons and holes are similar to those in a two-dimensional electron gas. The higher-energy conduction states and the deeper-energy valence ones behave similarly in the available deexcitation channels and have a similar dependence of decay rate on the wave vector.