Logic Design and Power Optimization of Floating-Point Multipliers.

Bai, Na; Li, Hang; Lv, Jiming; Yang, Shuai; Xu, Yaohua

Bai, Na; Li, Hang; Lv, Jiming; Yang, Shuai; Xu, Yaohua.

Afiliación

Bai N; Key Laboratory of Computational Intelligence and Signal Processing, Ministry of Education (Anhui University), School of Integrated Circuit, Anhui University, School of Electronic Information Engineering, Anhui University, Hefei 230601, China.
Li H; Key Laboratory of Computational Intelligence and Signal Processing, Ministry of Education (Anhui University), School of Integrated Circuit, Anhui University, School of Electronic Information Engineering, Anhui University, Hefei 230601, China.
Lv J; Key Laboratory of Computational Intelligence and Signal Processing, Ministry of Education (Anhui University), School of Integrated Circuit, Anhui University, School of Electronic Information Engineering, Anhui University, Hefei 230601, China.
Yang S; Key Laboratory of Computational Intelligence and Signal Processing, Ministry of Education (Anhui University), School of Integrated Circuit, Anhui University, School of Electronic Information Engineering, Anhui University, Hefei 230601, China.
Xu Y; Key Laboratory of Computational Intelligence and Signal Processing, Ministry of Education (Anhui University), School of Integrated Circuit, Anhui University, School of Electronic Information Engineering, Anhui University, Hefei 230601, China.

Comput Intell Neurosci ; 2022: 6949846, 2022.

Article en En | MEDLINE | ID: mdl-35035464

Asunto(s)

Algoritmos; Lenguaje; Lógica

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Texto completo: 1 Banco de datos: MEDLINE Asunto principal: Algoritmos / Lenguaje Idioma: En Revista: Comput Intell Neurosci Asunto de la revista: INFORMATICA MEDICA / NEUROLOGIA Año: 2022 Tipo del documento: Article País de afiliación: China

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