A CMOS compatible thermoelectric device made of crystalline silicon membranes with nanopores.

Herein, we report the use of nanostructured crystalline silicon as a thermoelectric material and its integration into thermoelectric devices. The proof-of-concept relies on the partial suppression of lattice thermal conduction by introducing pores with dimensions scaling between the electron mean free path and the phonon mean free path. In other words, we artificially aimed at the well-known 'electron crystal and phonon glass' trade-off targeted in thermoelectricity. The devices were fabricated using CMOS-compatible processes and exhibited power generation up to 5.5 mW cm-2under a temperature difference of 280 K. These numbers demonstrate the capability to power autonomous devices with environmental heat sources using silicon chips of centimeter square dimensions. We also report the possibility of using the developed devices for integrated thermoelectric cooling.

Thermoelectric characterization of crystalline nano-patterned silicon membranes.

Research towards efficient and environmentally friendly thermoelectrics proposes silicon nanostructures as possible candidates through reduction of the phononic thermal conductivity. However, there is scarce literature about experimental measurements of the thermoelectric figure-of-merit zT on actual crystalline silicon devices. This article reports on the fabrication and full thermoelectric characterization of crystalline 60 nm thick membranes. To that end, an experiment with four types of built-in devices was designed using a silicon-on-insulator substrate to extract the Seebeck coefficient, electrical conductivity and thermal conductivity. The results show indeed a reduced thermal conductivity of 31 W m-1 K-1 for a 60 nm thick Si membrane and κ = 18 W m-1 K-1 for a porous Si membrane. This reflects an 88% reduction in thermal conductivity compared to the bulk Si material and a 42% reduction compared to plain Si membranes. In terms of power generation, the power factor of the fabricated devices surpasses that of state-of-the-art silicon thin films at room temperature. Notably, a zT figure of merit of 0.04 is reported for a 60 nm thick phonon-engineered Si membrane, which is considerably higher than that of bulk Si(0.001) but lower than previously reported results on other types of nano-objects.

Nature-based solution enhances resilience to flooding and catalyzes multi-benefits in coastal cities in the Global South.

Coastal cities are facing a rise in groundwater levels induced by sea level rise, further triggering saturation excess flooding where groundwater levels reach the topographic surface or reduce the storage capacity of the soil, thus stressing the existing infrastructure. Lowering groundwater levels is a priority for sustaining the long-term livelihood of coastal cities. In the absence of studies assessing the possibility of using tree-planting as a measure of alleviating saturation excess flooding in the context of rising groundwater levels, the multi-benefit nature of tree-planting programs as sustainable Nature-based solutions (NBSs) in coastal cities in the Global South is discussed. In environments where groundwater is shallow, trees uptake groundwater or reduce groundwater recharge, thereby contributing to lower groundwater levels and increasing the unsaturated zone thickness, further reducing the risk of saturation excess flooding. Tree-planting programs represent long-term solutions sustained by environmental factors that are complementary to conventional engineering solutions. The multi-benefit nature of such NBSs and the expected positive environmental, economic, and social outcomes make them particularly promising. Wide social acceptance was identified as crucial for the long-term success of any tree-planting program, as the social factor plays a major role in addressing most weaknesses and threats of the solution. In the case of Nouakchott City (Mauritania), where a rise in groundwater levels has led to permanent saturation excess flooding, a tree-planting program has the potential to lower the groundwater levels, thereby reducing flooding during the rainy season.

Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories.

We present a new fully self-aligned single-electron memory with a single pair of nano floating gates, made of different materials (Si and Ge). The energy barrier that prevents stored charge leakage is induced not only by quantum effects but also by the conduction-band offset that arises between Ge and Si. The dimensions and position of each floating gate are well-defined and controlled. The devices exhibit a long retention time and single-electron injection at room temperature.

The good, the bad and the ugly polishing: Effect of abrasive size on standardless EDS analysis of Portland cement clinker's calcium silicates.

Standardless Energy dispersive spectroscopy (EDS) on polished samples of Portland cement clinker is routinely performed both for unhydrated phases as well as in cement pastes. Typically, the calcium to silica ratio is investigated. EDS analyses are highly dependent on the polishing quality of the sample. It is thus worth studying the Ca/Si ratios of cement phases in a clinker since they can be used as a reference. Indeed, alite (Ca3SiO5 or C3S in cement chemistry notation) and belite (Ca2SiO4 or C2S) should have an atomic Ca/Si ratio of 3 and 2, respectively. EDS carried out under the scanning electron microscope (SEM) is routinely used on polished samples to assess the composition of such phases. In the present study, Ca/Si ratios are investigated on a commercial clinker polished at various steps (6, 3, 1 and 0.25 µm diamond pastes, 0.05 µm alumina). All along the polishing process, ratios are coherent with theoretical ones and with the reference ones obtained by electron probe microanalysis (EMPA) in the present study.

Realization of vertical silicon nanowire networks with an ultra high density using a top-down approach.

In this paper, we demonstrate the top-down fabrication of vertical silicon nanowires networks with an ultra high density (4 x 10(10) cm(-2)), a yield of 100%, and a precise control of both diameter and location. Firstly, dense and well-defined networks of nanopillars have been patterned by e-beam lithography using a negative tone e-beam resist Hydrogen SylsesQuioxane (HSQ). A very high contrast has been obtained using a high acceleration voltage (100 kV), very small beam size at a current of 100 pA and a concentrated developer, 25% Tetramethylammonium Hydroxide. The patterns were transferred by reactive ion etching. Using chlorine based plasma chemistry and low pressure, etching anisotropy was guaranteed while avoiding the so-called 'grass effect'. This approach enabled the production of vertical silicon nanowires networks with a 20 nm diameter and a pitch of 30 nm. Lastly, the self-limited oxidation phenomenon in 1D structure has been used to perfectly control the shrinking of NWs and to obtain a Si surface free of defects induced by reactive ion etching. The silicon nanowires networks have been tapered by wet oxidation (850 degrees C) down to a diameter of 10 nm with a high aspect ratio 11.

Oxidation-assisted graphene heteroepitaxy on copper foil.

We propose an innovative, easy-to-implement approach to synthesize aligned large-area single-crystalline graphene flakes by chemical vapor deposition on copper foil. This method doubly takes advantage of residual oxygen present in the gas phase. First, by slightly oxidizing the copper surface, we induce grain boundary pinning in copper and, in consequence, the freezing of the thermal recrystallization process. Subsequent reduction of copper under hydrogen suddenly unlocks the delayed reconstruction, favoring the growth of centimeter-sized copper (111) grains through the mechanism of abnormal grain growth. Second, the oxidation of the copper surface also drastically reduces the nucleation density of graphene. This oxidation/reduction sequence leads to the synthesis of aligned millimeter-sized monolayer graphene domains in epitaxial registry with copper (111). The as-grown graphene flakes are demonstrated to be both single-crystalline and of high quality.

Characterization of ultrathin SOI film and application to short channel MOSFETs.

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.