Photophysics and Electronic Structure of Lateral Graphene/MoS2 and Metal/MoS2 Junctions.

Integration of semiconducting transition metal dichalcogenides (TMDs) into functional optoelectronic circuitries requires an understanding of the charge transfer across the interface between the TMD and the contacting material. Here, we use spatially resolved photocurrent microscopy to demonstrate electronic uniformity at the epitaxial graphene/molybdenum disulfide (EG/MoS2) interface. A 10× larger photocurrent is extracted at the EG/MoS2 interface when compared to the metal (Ti/Au)/MoS2 interface. This is supported by semi-local density functional theory (DFT), which predicts the Schottky barrier at the EG/MoS2 interface to be ∼2× lower than that at Ti/MoS2. We provide a direct visualization of a 2D material Schottky barrier through combination of angle-resolved photoemission spectroscopy with spatial resolution selected to be ∼300 nm (nano-ARPES) and DFT calculations. A bending of ∼500 meV over a length scale of ∼2-3 µm in the valence band maximum of MoS2 is observed via nano-ARPES. We explicate a correlation between experimental demonstration and theoretical predictions of barriers at graphene/TMD interfaces. Spatially resolved photocurrent mapping allows for directly visualizing the uniformity of built-in electric fields at heterostructure interfaces, providing a guide for microscopic engineering of charge transport across heterointerfaces. This simple probe-based technique also speaks directly to the 2D synthesis community to elucidate electronic uniformity at domain boundaries alongside morphological uniformity over large areas.

Deconvoluting the Photonic and Electronic Response of 2D Materials: The Case of MoS2.

Evaluating and tuning the properties of two-dimensional (2D) materials is a major focus of advancing 2D science and technology. While many claim that the photonic properties of a 2D layer provide evidence that the material is "high quality", this may not be true for electronic performance. In this work, we deconvolute the photonic and electronic response of synthetic monolayer molybdenum disulfide. We demonstrate that enhanced photoluminescence can be robustly engineered via the proper choice of substrate, where growth of MoS2 on r-plane sapphire can yield >100x enhancement in PL and carrier lifetime due to increased molybdenum-oxygen bonding compared to that of traditionally grown MoS2 on c-plane sapphire. These dramatic enhancements in optical properties are similar to those of super-acid treated MoS2, and suggest that the electronic properties of the MoS2 are also superior. However, a direct comparison of the charge transport properties indicates that the enhanced PL due to increased Mo-O bonding leads to p-type compensation doping, and is accompanied by a 2x degradation in transport properties compared to MoS2 grown on c-plane sapphire. This work provides a foundation for understanding the link between photonic and electronic performance of 2D semiconducting layers, and demonstrates that they are not always correlated.

Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.

Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices).

Characterization of graphene films and transistors grown on sapphire by metal-free chemical vapor deposition.

We present a novel method for the direct metal-free growth of graphene on sapphire that yields high quality films comparable to that of graphene grown on SiC by sublimation. Graphene is synthesized on sapphire via the simple decomposition of methane at 1425-1600 °C. Film quality was found to be a strong function of growth temperature. The thickness, structure, interface characteristics, and electrical transport properties were characterized in order to understand the utility of this material for electronic devices. Graphene synthesized on sapphire is found to be strain relieved, with no evidence of an interfacial buffer layer. There is a strong correlation between the graphene structural quality and carrier mobility. Room temperature Hall effect mobility values were as high as 3000 cm(2)/(V s), while measurements at 2 K reached values of 10,500 cm(2)/(V s). These films also display evidence of the quantum Hall effect. Field effect transistors fabricated from this material had a typical current density of 200 mA/mm and transconductance of 40 mS/mm indicating that material performance may be comparable to graphene on SiC.

Enhanced transport and transistor performance with oxide seeded high-κ gate dielectrics on wafer-scale epitaxial graphene.

We explore the effect of high-κ dielectric seed layer and overlayer on carrier transport in epitaxial graphene. We introduce a novel seeding technique for depositing dielectrics by atomic layer deposition that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Additionally, high-κ seeded dielectrics are shown to produce superior transistor performance relative to low-κ seeded dielectrics and the presence of heterogeneous seed/overlayer structures is found to be detrimental to transistor performance, reducing effective mobility by 30-40%. The direct deposition of high-purity oxide seed represents the first robust method for the deposition of uniform atomic layer deposited dielectrics on epitaxial graphene that improves carrier transport.

Epitaxial graphene transistors: enhancing performance via hydrogen intercalation.

We directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. Upon successful buffer elimination, carrier mobility increases from an average of 800 cm(2)/(V s) to >2000 cm(2)/(V s). Additionally, graphene transistor current saturation increases from 750 to >1300 mA/mm, and transconductance improves from 175 mS/mm to >400 mS. Finally, we report a 10× improvement in the extrinsic current gain response of graphene transistors with optimal extrinsic current-gain cutoff frequencies of 24 GHz.

Epitaxial graphene materials integration: effects of dielectric overlayers on structural and electronic properties.

We present the integration of epitaxial graphene with thin film dielectric materials for the purpose of graphene transistor development. The impact on epitaxial graphene structural and electronic properties following deposition of Al(2)O(3), HfO(2), TiO(2), and Ta(2)O(5) varies based on the choice of dielectric and deposition parameters. Each dielectric film requires the use of a nucleation layer to ensure uniform, continuous coverage on the graphene surface. Graphene quality degrades most severely following deposition of Ta(2)O(5), while the deposition if TiO(2) appears to improve the graphene carrier mobility. Finally, we discuss the potential of dielectric stack engineering for improved transistor performance.

Nucleation of epitaxial graphene on SiC(0001).

A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.