Future prospects of NAND flash memory technology--the evolution from floating gate to charge trapping to 3D stacking.

NAND Flash memory has scaled at phenomenal speed in the last decade and conventional floating gate (FG) Flash memory has now commenced volume production in the 2X nm node. Despite this stunning success, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (Multi-level Cell, or more than one bit storage per cell) storage. The simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels) also make CT suitable for 3D stacking. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1X nm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as TANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues.

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device.

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.