Hybrid 2D-CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2-Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D-CMOS hybrid microchips for memristive applications-CMOS stands for complementary metal-oxide-semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

A compute-in-memory chip based on resistive random-access memory.

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Fully hardware-implemented memristor convolutional neural network.

Memristor-enabled neuromorphic computing systems provide a fast and energy-efficient approach to training neural networks1-4. However, convolutional neural networks (CNNs)-one of the most important models for image recognition5-have not yet been fully hardware-implemented using memristor crossbars, which are cross-point arrays with a memristor device at each intersection. Moreover, achieving software-comparable results is highly challenging owing to the poor yield, large variation and other non-ideal characteristics of devices6-9. Here we report the fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs, which integrate eight 2,048-cell memristor arrays to improve parallel-computing efficiency. In addition, we propose an effective hybrid-training method to adapt to device imperfections and improve the overall system performance. We built a five-layer memristor-based CNN to perform MNIST10 image recognition, and achieved a high accuracy of more than 96 per cent. In addition to parallel convolutions using different kernels with shared inputs, replication of multiple identical kernels in memristor arrays was demonstrated for processing different inputs in parallel. The memristor-based CNN neuromorphic system has an energy efficiency more than two orders of magnitude greater than that of state-of-the-art graphics-processing units, and is shown to be scalable to larger networks, such as residual neural networks. Our results are expected to enable a viable memristor-based non-von Neumann hardware solution for deep neural networks and edge computing.

Towards artificial general intelligence with hybrid Tianjic chip architecture.

There are two general approaches to developing artificial general intelligence (AGI)1: computer-science-oriented and neuroscience-oriented. Because of the fundamental differences in their formulations and coding schemes, these two approaches rely on distinct and incompatible platforms2-8, retarding the development of AGI. A general platform that could support the prevailing computer-science-based artificial neural networks as well as neuroscience-inspired models and algorithms is highly desirable. Here we present the Tianjic chip, which integrates the two approaches to provide a hybrid, synergistic platform. The Tianjic chip adopts a many-core architecture, reconfigurable building blocks and a streamlined dataflow with hybrid coding schemes, and can not only accommodate computer-science-based machine-learning algorithms, but also easily implement brain-inspired circuits and several coding schemes. Using just one chip, we demonstrate the simultaneous processing of versatile algorithms and models in an unmanned bicycle system, realizing real-time object detection, tracking, voice control, obstacle avoidance and balance control. Our study is expected to stimulate AGI development by paving the way to more generalized hardware platforms.

Memristive Behaviors Dominated by Reversible Nucleation Dynamics of Phase-Change Nanoclusters.

One of the important steps for realizing artificial intelligence is identifying elementary units that are beneficial for neural network construction. A type of memristive behavior in which phase-change nanoclusters nucleate adaptively in two adjacent dielectric layers with distinct distribution patterns is demonstrated. This memristive system responds in potentiation to increased stimulation strength and fire action potential after threshold stimulation. Reversible nucleation of phase-change nanoclusters is confirmed after both in situ and ex situ examinations using high-resolution transmission electron microscopy. The dynamics at the nanoscale level dominates the actions of the two dielectric layers. The oscillation response over a long period is due to the competition between crystalline and amorphous phases in the layer near the bottom electrode. Weight mutation, that is, action potential firing, is caused by the blockage of the filament in the layer near the top electrode. The memristive system is compact and able to execute complicated functions of a complete neuron and performs an important role in neuromorphic computing.

Observation of the antiferromagnetic spin Hall effect.

The discovery of the spin Hall effect1 enabled the efficient generation and manipulation of the spin current. More recently, the magnetic spin Hall effect2,3 was observed in non-collinear antiferromagnets, where the spin conservation is broken due to the non-collinear spin configuration. This provides a unique opportunity to control the spin current and relevant device performance with controllable magnetization. Here, we report a magnetic spin Hall effect in a collinear antiferromagnet, Mn2Au. The spin currents are generated at two spin sublattices with broken spatial symmetry, and the antiparallel antiferromagnetic moments play an important role. Therefore, we term this effect the 'antiferromagnetic spin Hall effect'. The out-of-plane spins from the antiferromagnetic spin Hall effect are favourable for the efficient switching of perpendicular magnetized devices, which is required for high-density applications. The antiferromagnetic spin Hall effect adds another twist to the atomic-level control of spin currents via the antiferromagnetic spin structure.

Residual D2NN: training diffractive deep neural networks via learnable light shortcuts.

The diffractive deep neural network (D2NN) has demonstrated its importance in performing various all-optical machine learning tasks, e.g., classification, segmentation, etc. However, deeper D2NNs that provide higher inference complexity are more difficult to train due to the problem of gradient vanishing. We introduce the residual D2NNs (Res-D2NN), which enables us to train substantially deeper diffractive networks by constructing diffractive residual learning blocks to learn the residual mapping functions. Unlike the existing plain D2NNs, Res-D2NNs contribute to the design of a learnable light shortcut to directly connect the input and output between optical layers. Such a shortcut offers a direct path for gradient backpropagation in training, which is an effective way to alleviate the gradient vanishing issue on very deep diffractive neural networks. Experimental results on image classification and pixel super-resolution demonstrate the superiority of Res-D2NNs over the existing plain D2NN architectures.

Amplitude and frequency modulation based on memristor-controlled spin nano-oscillators.

Spin transfer nano-oscillators (STNOs) are a new type of radio frequency (RF) oscillators that utilize the current-induced magnetization precession in a magnetic tunnel junction device to generate high frequency microwave signal. Since both the frequency and the amplitude of STNOs can be tuned by changing the current, they are potentially used for amplitude shift keying and frequency shift keying modulation without the need for an RF mixer, which leads to compact RF components. In this letter, a novel strategy is proposed to modulate the frequency and the amplitude by memristor-controlled spin nano-oscillators, whereby the STNO is responsible for microwave emitting and memristor serves as a current regulator which further modulates the frequency and amplitude. In addition, the I-V curves show that a multilevel resistance behavior can also be achieved in the same architecture.

Electrode-induced digital-to-analog resistive switching in TaO x -based RRAM devices.

In RRAM devices, electrodes play a significant role during the switching process. In this paper, different top electrodes are used for TaO y /Ta2O5-x /AlO σ triple-oxide-layer devices. Top electrode-induced digital resistive switching to analog resistive switching was observed. For Pt top electrode (TE) devices, abrupt digital resistive switching behavior was observed, while Al TE devices showed gradual analog resistive switching behavior. Devices with various AlO σ thicknesses and sizes were fabricated and characterized to evaluate the reliability of the analog resistive switching. The physical mechanisms responsible for this electrode-induced resistive switching behavior were discussed.

HfO2/Al2O3 multilayer for RRAM arrays: a technique to improve tail-bit retention.

In this work, the HfO2/Al2O3 multilayer structure is applied for RRAM arrays. Compared to HfO2 RRAM, the data retention failure of tail bits is suppressed significantly, especially for the high resistance state (HRS). The retention of tail bits is studied in detail by temperature simulation and crystallization analysis. We attribute the improvement of tail-bit retention to the decreased oxygen ion diffusivity caused by the Al2O3 layer. Furthermore, the HfO2/Al2O3 multilayer structure exhibits higher crystallization temperature, thus leading to fewer grain boundaries around the filament during the operations. With fewer grain boundaries, oxygen ion diffusion is suppressed, leading to fewer tail bits and better retention.

Double-Balanced Graphene Integrated Mixer with Outstanding Linearity.

A monolithic double-balanced graphene mixer integrated circuit (IC) has been successfully designed and fabricated. The IC adopted the cross-coupled resistive mixer topology, integrating four 500 nm-gate-length graphene field-effect transistors (GFETs), four on-chip inductors, and four on-chip capacitors. Passive-first-active-last fabrication flow was developed on 200 mm CMOS wafers. CMOS back-end-of-line processes were utilized to realize most fabrication steps followed by GFET-customized processes. Test results show excellent output spectrum purity with suppressed radio frequency (RF) and local oscillation (LO) signals feedthroughs, and third-order input intercept (IIP3) reaches as high as 21 dBm. The results are compared with a fabricated single-GEFT mixer, which generates IIP3 of 16.5 dBm. Stand-alone 500 nm-gate-length GFETs feature cutoff frequency 22 GHz and maximum oscillation frequency 20.7 GHz RF performance. The double-balanced mixer IC operated with off-chip baluns realizing a print-circuit-board level electronic system. It demonstrates graphene's potential to compete with other semiconductor technologies in RF front-end applications.

Stable self-compliance resistive switching in AlOδ/Ta2O(5-x)/TaOy triple layer devices.

Stable self-compliance property was observed in the AlOδ/Ta2O(5-x)/TaOy triple-layer resistive random access memory structure. The impact of AlOδ barrier layer was studied with different thicknesses. Endurance of more than 10(10) cycles and data retention for more than 3 h at 125 °C were demonstrated. All the measurements were carried out without external current compliance and no hard breakdown was observed. Systematic analysis reveals the self-compliance property is due to the built-in series resistance of the thin AlOδ barrier layer. A model is proposed to explain this self-compliance property.

Atomistic study of dynamics for metallic filament growth in conductive-bridge random access memory.

The growth dynamics for metallic filaments in conductive-bridge resistive-switching random access memory (CBRAM) are studied using the kinetic Monte Carlo (KMC) method. The physical process at the atomistic level is revealed in explaining the experimental observation that filament growth can originate at either the cathode or the anode. The statistical nature of the filament growth is best shown by the random topography of dendrite-like conductive paths obtained. Critical material properties, such as charged-particle mobility in the switching layer of a solid electrolyte or a dielectric, are mapped to KMC model parameters through activation energy, etc. The accuracy of the simulator is established by the good agreement between the simulated forming time and the measured data.

Acoustic-driven magnetic skyrmion motion.

Magnetic skyrmions have great potential for developing novel spintronic devices. The electrical manipulation of skyrmions has mainly relied on current-induced spin-orbit torques. Recently, it was suggested that the skyrmions could be more efficiently manipulated by surface acoustic waves (SAWs), an elastic wave that can couple with magnetic moment via the magnetoelastic effect. Here, by designing on-chip piezoelectric transducers that produce propagating SAW pulses, we experimentally demonstrate the directional motion of Néel-type skyrmions in Ta/CoFeB/MgO/Ta multilayers. We find that the shear horizontal wave effectively drives the motion of skyrmions, whereas the elastic wave with longitudinal and shear vertical displacements (Rayleigh wave) cannot produce the motion of skyrmions. A longitudinal motion along the SAW propagation direction and a transverse motion due to topological charge are simultaneously observed and further confirmed by our micromagnetic simulations. This work demonstrates that acoustic waves could be another promising approach for manipulating skyrmions, which could offer new opportunities for ultra-low power skyrmionics.

Voltage control of multiferroic magnon torque for reconfigurable logic-in-memory.

Magnons, bosonic quasiparticles carrying angular momentum, can flow through insulators for information transmission with minimal power dissipation. However, it remains challenging to develop a magnon-based logic due to the lack of efficient electrical manipulation of magnon transport. Here we show the electric excitation and control of multiferroic magnon modes in a spin-source/multiferroic/ferromagnet structure. We demonstrate that the ferroelectric polarization can electrically modulate the magnon-mediated spin-orbit torque by controlling the non-collinear antiferromagnetic structure in multiferroic bismuth ferrite thin films with coupled antiferromagnetic and ferroelectric orders. In this multiferroic magnon torque device, magnon information is encoded to ferromagnetic bits by the magnon-mediated spin torque. By manipulating the two coupled non-volatile state variables-ferroelectric polarization and magnetization-we further present reconfigurable logic operations in a single device. Our findings highlight the potential of multiferroics for controlling magnon information transport and offer a pathway towards room-temperature voltage-controlled, low-power, scalable magnonics for in-memory computing.

Three-Dimensional Reconstruction of Conductive Filaments in HfOx -Based Memristor.

HfOx -based memristor has been studied extensively as one of the most promising memories for the excellent nonvolatile data storage and computing-in-memory capabilities. However, the resistive switching mechanism, relying on the formation and rupture of conductive filaments (CFs) during device operations, is still under debate. In this work, the CFs with different morphologies after different operations-forming, set, and reset-are clearly revealed for the first time by 3D reconstruction of conductive atomic force microscopy (c-AFM) images. Intriguingly, multiple CFs are successfully observed in HfOx -based memristor devices with three different resistive states. CFs after forming, set, and reset exhibit the typical morphologies of hourglass, inverted-cone, and short-cone, respectively. The rupture location of CFs after the reset operation is also observed clearly. These findings reveal the microscopic behaviors underlying the resistive switching, which could pave the road to design and optimize oxide-based memristors for both memory and computing applications.

A Memristors-Based Dendritic Neuron for High-Efficiency Spatial-Temporal Information Processing.

Diverse microscopic ionic dynamics help mediate the ability of a biological neural network to handle complex tasks with low energy consumption. Thus, rich internal ionic dynamics in memristors based on transition metal oxide are expected to provide a unique and useful platform for implementing energy-efficient neuromorphic computing. To this end, a titanium oxide (TiOx )-based interface-type dynamic memristor and an niobium oxide (NbOx )-based Mott memristor are integrated as an artificial dendrite and spike-firing soma, respectively, to construct a dendritic neuron unit for realizing high-efficiency spatial-temporal information processing. Further, a dendritic neural network is hardware-implemented for spatial-temporal information processing to highlight the computational advantages achieved by incorporating dendritic functions in the network. Human motion recognition is demonstrated using the Nanyang Technological University-Red Green Blue (NTU-RGB) dataset as a benchmark spatial-temporal task; it shows a nearly 20% improvement in accuracy for the memristors-based hardware incorporating dendrites and a 1000× advantage in power efficiency compared to that of the graphics processing unit (GPU). The dendritic neuron developed in this study can be considered a critical building block for implementing more bio-plausible neural networks that can manage complex spatial-temporal tasks with high efficiency.

Energy-efficient high-fidelity image reconstruction with memristor arrays for medical diagnosis.

Medical imaging is an important tool for accurate medical diagnosis, while state-of-the-art image reconstruction algorithms raise critical challenges in massive data processing for high-speed and high-quality imaging. Here, we present a memristive image reconstructor (MIR) to greatly accelerate image reconstruction with discrete Fourier transformation (DFT) by computing-in-memory (CIM) with memristor arrays. A high-accuracy quasi-analogue mapping (QAM) method and generic complex matrix transfer (CMT) scheme was proposed to improve the mapping precision and transfer efficiency, respectively. High-fidelity magnetic resonance imaging (MRI) and computed tomography (CT) image reconstructions were demonstrated, achieving software-equivalent qualities and DICE scores after segmentation with nnU-Net algorithm. Remarkably, our MIR exhibited 153× and 79× improvements in energy efficiency and normalized image reconstruction speed, respectively, compared to graphics processing unit (GPU). This work demonstrates MIR as a promising high-fidelity image reconstruction platform for future medical diagnosis, and also largely extends the application of memristor-based CIM beyond artificial neural networks.

Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.