Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique.

With the application of stitching technology in large-pixel-array CMOS image sensors, the problem of non-synchronized output signals from pixel array bilateral driver circuits has become progressively more serious and has led to the DC perforation of bilateral driver circuits, while conventional clock tree synchronization design methodology does not apply to stitching technology. Therefore, this paper analyses reasons for the inconsistency in the output signals of bilateral driving circuits and proposes a synchronous driving method applicable to stitching pixel arrays based on the idea of on-chip output signal delay detection and calibration. This method detects and corrects the non-synchrony of the row driver output signals on both sides according to changes in the operating environment of the chip. This method is characterized by a simple structure and high reliability. Finally, based on the 55 nm stitching process, simulations are carried out in a CMOS image sensor with a chip area of 77 mm × 84 mm to verify that this method is feasible. This large image sensor with a 150 M pixel array has a frame rate of over 10 FPS.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor.

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 µW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

High Dynamic Pixel Structure Based on an Adaptive Integrating Capacitor.

Infrared image sensing technology has received widespread attention due to its advantages of not being affected by the environment, good target recognition, and high anti-interference ability. However, with the improvement of the integration of the infrared focal plane, the dynamic range of the photoelectric system is difficult to improve, that is, the restrictive trade-off between noise and full well capacity is particularly prominent. Since the capacitance of the inversion MOS capacitor changes with the gate-source voltage adaptively, the inversion MOS capacitor is used as the capacitor in the infrared pixel circuit, which can solve the contradiction between noise in low light and full well capacity in high light. To this end, a highly dynamic pixel structure based on adaptive capacitance is proposed, so that the capacitance of the infrared image sensor can automatically change from 6.5 fF to 37.5 fF as the light intensity increases. And based on 55 nm CMOS process technology, the performance parameters of an infrared image sensor with a 12,288 × 12,288 pixel array are studied. The research results show that a small-size pixel of 5.5 µm × 5.5 µm has a large full well capacity of 1.31 Me- and a variable conversion gain, with a noise of less than 0.43 e- and a dynamic range of more than 130 dB.

High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement.

In order to solve the problem of limited linearity and frame rate in the large array infrared (IR) readout integrated circuit (ROIC), a high-linearity and high-speed readout method based on adaptive offset compensation and alternating current (AC) enhancement is proposed in this paper. The efficient correlated double sampling (CDS) method in pixels is used to optimize the noise characteristics of the ROIC and output CDS voltage to the column bus. An AC enhancement method is proposed to quickly establish the column bus signal, and an adaptive offset compensation method is used at the column bus terminal to eliminate the nonlinearity caused by the pixel source follower (SF). Based on the 55 nm process, the proposed method is comprehensively verified in an 8192 × 8192 IR ROIC. The results show that, compared with the traditional readout circuit, the output swing is increased from 2 V to 3.3 V, and the full well capacity is increased from 4.3 Me- to 6 Me-. The row time of the ROIC is reduced from 20 µs to 2 µs, and the linearity is improved from 96.9% to 99.98%. The overall power consumption of the chip is 1.6 W, and the single-column power consumption of the readout optimization circuit is 33 µW in the accelerated readout mode and 16.5 µW in the nonlinear correction mode.

Lensless light intensity model for quasi-spherical cell size measurement.

Quasi-spherical cell size measurement plays an important role in medical test. Traditional methods such as a microscope and a flow cytometer are either it depends on professionals and cannot be automated, or it is expensive and bulky, which are not suitable for point-of-care test. Lab-on-a-chip technology using the lensless imaging system gives a good solution for obtaining the quasi-spherical cell size. The diffraction effects and the low resolution are the two main problems faced by the lensless imaging system. In this paper, a lensless light intensity model for the quasi-spherical cell size measurement is given. First, the diffraction characteristics of a quasi-spherical cell edge are given. Then, a diffraction model at an arc edge is constructed based on the Fresnel diffraction at a straight edge. Using the diffraction model at an arc edge, we explained the mechanism of the formation of the quasi-spherical cell diffraction fringes. Finally, the light intensity of the first bright ring of the quasi-spherical cell diffraction pattern is used to achieve quasi-spherical cell size measurement. The required equipment and the measurement methods are extremely simple, very suitable for point-of-care test. The experimental results show that the proposed model can realize the statistical measurement of the quasi-spherical cells and the classification of the quasi-spherical cells with a difference of 1 [Formula: see text].

Measurement of red blood cell size based on a lensless imaging system.

The variability in the size of red blood cells (RBCs) is an important additional diagnostic parameter for diseases, which has been established as a part of the complete blood count (CBC). The CBC can be performed using an automated flow cytometer, but it is too bulky and expensive for point-of-care testing. A miniaturized lensless imaging system is a competitive modality for a CBC, that is small and inexpensive. There are two challenges in developing a lensless imaging system for taking the CBC, which make the measurement of the RBC size very difficult: the diffraction effect and the low resolution. In this paper, the RBC radius measurement is replaced with a diffraction ring radius measurement. The diffraction ring radius is much larger than the RBC radius. This feature can improve the imaging resolution. Based on Fresnel diffraction, the relationship between the radius of RBCs and the diffraction fringes is analyzed. Finally, a complete measurement algorithm for determining the RBC size based on the lensless imaging system is given, which can be used to measure the variability in the size of RBCs. In our experiment, the maximum error is less than 6.74%.

A Quantized CNN-Based Microfluidic Lensless-Sensing Mobile Blood-Acquisition and Analysis System.

This paper proposes a microfluidic lensless-sensing mobile blood-acquisition and analysis system. For a better tradeoff between accuracy and hardware cost, an integer-only quantization algorithm is proposed. Compared with floating-point inference, the proposed quantization algorithm makes a tradeoff that enables miniaturization while maintaining high accuracy. The quantization algorithm allows the convolutional neural network (CNN) inference to be carried out using integer arithmetic and facilitates hardware implementation with area and power savings. A dual configuration register group structure is also proposed to reduce the interval idle time between every neural network layer in order to improve the CNN processing efficiency. We designed a CNN accelerator architecture for the integer-only quantization algorithm and the dual configuration register group and implemented them in field-programmable gate arrays (FPGA). A microfluidic chip and mobile lensless sensing cell image acquisition device were also developed, then combined with the CNN accelerator to build the mobile lensless microfluidic blood image-acquisition and analysis prototype system. We applied the cell segmentation and cell classification CNN in the system and the classification accuracy reached 98.44%. Compared with the floating-point method, the accuracy dropped by only 0.56%, but the area decreased by 45%. When the system is implemented with the maximum frequency of 100 MHz in the FPGA, a classification speed of 17.9 frames per second (fps) can be obtained. The results show that the quantized CNN microfluidic lensless-sensing blood-acquisition and analysis system fully meets the needs of current portable medical devices, and is conducive to promoting the transformation of artificial intelligence (AI)-based blood cell acquisition and analysis work from large servers to portable cell analysis devices, facilitating rapid early analysis of diseases.

A soft decoding algorithm and hardware implementation for the visual prosthesis based on high order soft demodulation.

BACKGROUND: High order modulation and demodulation technology can solve the frequency requirement between the wireless energy transmission and data communication. In order to achieve reliable wireless data communication based on high order modulation technology for visual prosthesis, this work proposed a Reed-Solomon (RS) error correcting code (ECC) circuit on the basis of differential amplitude and phase shift keying (DAPSK) soft demodulation. Firstly, recognizing the weakness of the traditional DAPSK soft demodulation algorithm based on division that is complex for hardware implementation, an improved phase soft demodulation algorithm for visual prosthesis to reduce the hardware complexity is put forward. Based on this new algorithm, an improved RS soft decoding method is hence proposed. In this new decoding method, the combination of Chase algorithm and hard decoding algorithms is used to achieve soft decoding. In order to meet the requirements of implantable visual prosthesis, the method to calculate reliability of symbol-level based on multiplication of bit reliability is derived, which reduces the testing vectors number of Chase algorithm. The proposed algorithms are verified by MATLAB simulation and FPGA experimental results. During MATLAB simulation, the biological channel attenuation property model is added into the ECC circuit. RESULTS: The data rate is 8 Mbps in the MATLAB simulation and FPGA experiments. MATLAB simulation results show that the improved phase soft demodulation algorithm proposed in this paper saves hardware resources without losing bit error rate (BER) performance. Compared with the traditional demodulation circuit, the coding gain of the ECC circuit has been improved by about 3 dB under the same BER of [Formula: see text]. The FPGA experimental results show that under the condition of data demodulation error with wireless coils 3 cm away, the system can correct it. The greater the distance, the higher the BER. Then we use a bit error rate analyzer to measure BER of the demodulation circuit and the RS ECC circuit with different distance of two coils. And the experimental results show that the RS ECC circuit has about an order of magnitude lower BER than the demodulation circuit when under the same coils distance. Therefore, the RS ECC circuit has more higher reliability of the communication in the system. CONCLUSIONS: The improved phase soft demodulation algorithm and soft decoding algorithm proposed in this paper enables data communication that is more reliable than other demodulation system, which also provide a significant reference for further study to the visual prosthesis system.

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels.

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

Red blood cell recognition and posture estimation in microfluidic chip based on lensless imaging.

On the one hand, lensless imaging technology has become one of the key technologies to achieve point-of-care testing; on the other hand, microfluidic technology has shown great application potential in the field of biological detection. Using mainstream lensless imaging technology to achieve biological cell imaging in microfluidic chips has technical limitations. In particular, it is more difficult to achieve lensless imaging for non-spherical cells in microfluidic chips such as red blood cells. Achieving red blood cell recognition and posture estimation in a microfluidic chip under the lensless imaging, combined with mainstream lensless imaging technology, can provide more effective red blood cell morphological parameters for medical diagnosis. In this paper, the method for red blood cell recognition and posture estimation in microfluidic chips based on lensless imaging is given. First, the relevant theoretical basis is introduced. Then, the models of red blood cell recognition and posture estimation in microfluidic chips based on lensless imaging are given. The effect of red blood cell flipping on lensless imaging is analyzed in the modeling process. Finally, the effectiveness of the proposed method is verified by experiments. Experiments show that the proposed method can well achieve red blood cell recognition and posture estimation through the shape characteristics of red blood cells.

Adaptive Parameter Model for Quasi-Spherical Cell Size Measurement Based on Lensless Imaging System.

Many biological cells appear quasi-spherical, such as red blood cells, white blood cells, egg cells, cancer cells, etc. Cell size is an important basis for medical diagnosis. The traditional method is to use a microscope or flow cytometer to obtain the cell size. Either it depends on professionals and cannot be automated, or it is expensive and bulky, which are not suitable for point-of-care test. Lab-on-a-chip technology using a lensless imaging system gives a better solution for obtaining the cell size. In order to deal with the diffraction in the lensless imaging system, the distance between the light source and the cell, the distance between the cell and the CMOS image sensor and optical wavelength need to be accurately measured or controlled, which will greatly increase the complexity of the system, making it difficult to truly apply to point-of-care test. In this paper, an adaptive parameter model for quasi-spherical cell size measurement based on lensless imaging system is given. First, the diffraction theory used in the model is explained. Then, the adaptive algorithm of the system parameter is given. To illustrate the practicality of the algorithm, a quasi-spherical cell size measurement method and a super-resolution algorithm are given. Finally, the experiment proves that the adaptive parameter model is effective can meet the needs of quasi-spherical cell size measurement.

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture.

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 µW, 59.7 µW and 71.1 µW. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

A super-resolution scanning algorithm for lensless microfluidic imaging using the dual-line array image sensor.

The lensless optical fluid microscopy is of great significance to the miniaturization, portability and low cost development of cell detection instruments. However, the resolution of the cell image collected directly is low, because the physical pixel size of the image sensor is the same order of magnitude as the cell size. To solve this problem, this paper proposes a super-resolution scanning algorithm using a dual-line array sensor and a microfluidic chip. For dual-line array sensor images, the multi-group velocity and acceleration of cells flowing through the line array sensor are calculated. Then the reconstruction model of the super-resolution image is constructed with variable acceleration. By changing the angle between the line array image sensor and the direction of cell flow, the super-resolution image scanning and reconstruction are achieved in both horizontal and vertical directions. In addition, it is necessary to study the row by row extraction algorithm for cell foreground image. In this paper, the dual-line array sensor is implemented by adjusting the acquisition window of the image sensor with a pixel size of 2.2µm. When the tilt angle is 21 degrees, the equivalent pixel size is 0.79µm, improved 2.8 times, and after de-diffraction its average size error was 3.249%. As the angle decreases, the image resolution is higher, but the amount of information is less. This super-resolution scanning algorithm can be integrated on the chip and used with a microfluidic chip to realize on-chip instrument.

High-Precision Lens-Less Flow Cytometer on a Chip.

We present a flow cytometer on a microfluidic chip that integrates an inline lens-free holographic microscope. High-speed cell analysis necessitates that cells flow through the microfluidic channel at a high velocity, but the image sensor of the in-line holographic microscope needs a long exposure time. Therefore, to solve this problem, this paper proposes an S-type micro-channel and a pulse injection method. To increase the speed and accuracy of the hologram reconstruction, we improve the iterative initial constraint method and propose a background removal method. The focus images and cell concentrations can be accurately calculated by the developed method. Using whole blood cells to test the cell counting precision, we find that the cell counting error of the proposed method is less than 2%. This result shows that the on-chip flow cytometer has high precision. Due to its low price and small size, this flow cytometer is suitable for environments far away from laboratories, such as underdeveloped areas and outdoors, and it is especially suitable for point-of-care testing (POCT).

Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET.

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed.

An on-chip instrument for white blood cells classification based on a lens-less shadow imaging technique.

Routine blood tests provide important basic information for disease diagnoses. The proportions of three subtypes of white blood cells (WBCs), which are neutrophils, monocytes, lymphocytes, is key information for disease diagnosis. However, current instruments for routine blood tests, such as blood cell analyzers, flow cytometers, and optical microscopes, are cumbersome, time consuming and expensive. To make a smaller, automatic low-cost blood cell analyzer, much research has focused on a technique called lens-less shadow imaging, which can obtain microscopic images of cells in a lens-less system. Nevertheless, the efficiency of this imaging system is not satisfactory because of two problems: low resolution and imaging diffraction phenomena. In this paper, a novel method of classifying cells with the shadow imaging technique was proposed. It could be used for the classification of the three subtypes of WBCs, and the correlation of the results of classification between the proposed system and the reference system (BC-5180, Mindray) was 0.93. However, the instrument was only 10 × 10 × 10 cm, and the cost was less than $100. Depending on the lens-free shadow imaging technology, the main hardware could be integrated on a chip scale and could be called an on-chip instrument.