Simultaneous scanning tunneling microscopy and stress measurements to elucidate the origins of surface forces.

We have developed a new combined measurement system to investigate the underlying origins of forces on solid state surfaces from the viewpoint of atomic surface morphology. This system consists of two main parts: the measurements of force based on displacements and detailed atomic resolution observations of the surface morphology. The former involves a large sample cantilever and a capacitive detection method that provide sufficient resolution to detect changes of a few meV/atom or pN/atom at surfaces. For the latter, a scanning tunneling microscope was incorporated to observe structural changes occurring on the surface of the cantilever sample. Although this combined observation is not trivial, it was accomplished by carefully designing sample dimensions while suppressing the self-oscillation of the cantilever. To demonstrate the performance of this system a preliminary study of the room temperature adsorption of Br(2) on the clean Si(111)-7x7 surface is presented.

Large-scale parallel arrays of silicon nanowires via block copolymer directed self-assembly.

Extending the resolution and spatial proximity of lithographic patterning below critical dimensions of 20 nm remains a key challenge with very-large-scale integration, especially if the persistent scaling of silicon electronic devices is sustained. One approach, which relies upon the directed self-assembly of block copolymers by chemical-epitaxy, is capable of achieving high density 1 : 1 patterning with critical dimensions approaching 5 nm. Herein, we outline an integration-favourable strategy for fabricating high areal density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer nanopatterns with a L(0) (pitch) of 42 nm, on chemically pre-patterned surfaces. Parallel arrays (5 × 10(6) wires per cm) of uni-directional and isolated silicon nanowires on insulator substrates with critical dimension ranging from 15 to 19 nm were fabricated by using precision plasma etch processes; with each stage monitored by electron microscopy. This step-by-step approach provides detailed information on interfacial oxide formation at the device silicon layer, the polystyrene profile during plasma etching, final critical dimension uniformity and line edge roughness variation nanowire during processing. The resulting silicon-nanowire array devices exhibit Schottky-type behaviour and a clear field-effect. The measured values for resistivity and specific contact resistance were ((2.6 ± 1.2) × 10(5)Ωcm) and ((240 ± 80) Ωcm(2)) respectively. These values are typical for intrinsic (un-doped) silicon when contacted by high work function metal albeit counterintuitive as the resistivity of the starting wafer (∼10 Ωcm) is 4 orders of magnitude lower. In essence, the nanowires are so small and consist of so few atoms, that statistically, at the original doping level each nanowire contains less than a single dopant atom and consequently exhibits the electrical behaviour of the un-doped host material. Moreover this indicates that the processing successfully avoided unintentional doping. Therefore our approach permits tuning of the device steps to contact the nanowires functionality through careful selection of the initial bulk starting material and/or by means of post processing steps e.g. thermal annealing of metal contacts to produce high performance devices. We envision that such a controllable process, combined with the precision patterning of the aligned block copolymer nanopatterns, could prolong the scaling of nanoelectronics and potentially enable the fabrication of dense, parallel arrays of multi-gate field effect transistors.