Fabrication of a sub-10 nm silicon nanowire based ethanol sensor using block copolymer lithography.

This paper details the fabrication of ultrathin silicon nanowires (SiNWs) on a silicon-on-insulator (SOI) substrate as an electrode for the electro-oxidation and sensing of ethanol. The nanowire surfaces were prepared by a block copolymer (BCP) nanolithographic technique using low molecular weight symmetric poly(styrene)-block-poly(methyl methacrylate) (PS-b-PMMA) to create a nanopattern which was transferred to the substrate using plasma etching. The BCP orientation was controlled using a hydroxyl-terminated random polymer brush of poly(styrene)-random-poly(methyl methacrylate) (HO-PS-r-PMMA). TEM cross-sections of the resultant SiNWs indicate an anisotropic etch process with nanowires of sub-10 nm feature size. The SiNWs obtained by etching show high crystallinity and there is no evidence of defect inclusion or amorphous region production as a result of the pattern transfer process. The high density of SiNWs at the substrate surface allowed the fabrication of a sensor for cyclic voltammetric detection of ethanol. The sensor shows better sensitivity to ethanol and a faster response time compared to widely used polymer nanocomposite based sensors.

Nanoscale mapping of electrical resistivity and connectivity in graphene strips and networks.

In this article we map out the thickness dependence of the resistivity of individual graphene strips, from single layer graphene through to the formation of graphitic structures. We report exceptionally low resistivity values for single strips and demonstrate that the resistivity distribution for single strips is anomalously narrow when compared to bi- and trilayer graphene, consistent with the unique electronic properties of single graphene layers. In agreement with theoretical predictions, we show that the transition to bulklike resistivities occurs at seven to eight layers of graphene. Moreover, we demonstrate that the contact resistance between graphene flakes in a graphene network scales with the flake thickness and the implications for transparent conductor applications are discussed.

Surface energy driven agglomeration and growth of single crystal metal wires.

We introduce a novel wire growth technique that involves simply heating a multilayer film specifically designed to take advantage of the different surface energies of the substrate and film components. In all cases the high surface energy component is extruded as a single crystal nanowire. Moreover we demonstrate that patterning the bilayer film generates localized surface agglomeration waves during the anneal that can be exploited to position the grown wires. Examples of Au and Cu nanowire growth are presented, and the generalization of this method to other systems is discussed.

Large-scale parallel arrays of silicon nanowires via block copolymer directed self-assembly.

Extending the resolution and spatial proximity of lithographic patterning below critical dimensions of 20 nm remains a key challenge with very-large-scale integration, especially if the persistent scaling of silicon electronic devices is sustained. One approach, which relies upon the directed self-assembly of block copolymers by chemical-epitaxy, is capable of achieving high density 1 : 1 patterning with critical dimensions approaching 5 nm. Herein, we outline an integration-favourable strategy for fabricating high areal density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer nanopatterns with a L(0) (pitch) of 42 nm, on chemically pre-patterned surfaces. Parallel arrays (5 × 10(6) wires per cm) of uni-directional and isolated silicon nanowires on insulator substrates with critical dimension ranging from 15 to 19 nm were fabricated by using precision plasma etch processes; with each stage monitored by electron microscopy. This step-by-step approach provides detailed information on interfacial oxide formation at the device silicon layer, the polystyrene profile during plasma etching, final critical dimension uniformity and line edge roughness variation nanowire during processing. The resulting silicon-nanowire array devices exhibit Schottky-type behaviour and a clear field-effect. The measured values for resistivity and specific contact resistance were ((2.6 ± 1.2) × 10(5)Ωcm) and ((240 ± 80) Ωcm(2)) respectively. These values are typical for intrinsic (un-doped) silicon when contacted by high work function metal albeit counterintuitive as the resistivity of the starting wafer (∼10 Ωcm) is 4 orders of magnitude lower. In essence, the nanowires are so small and consist of so few atoms, that statistically, at the original doping level each nanowire contains less than a single dopant atom and consequently exhibits the electrical behaviour of the un-doped host material. Moreover this indicates that the processing successfully avoided unintentional doping. Therefore our approach permits tuning of the device steps to contact the nanowires functionality through careful selection of the initial bulk starting material and/or by means of post processing steps e.g. thermal annealing of metal contacts to produce high performance devices. We envision that such a controllable process, combined with the precision patterning of the aligned block copolymer nanopatterns, could prolong the scaling of nanoelectronics and potentially enable the fabrication of dense, parallel arrays of multi-gate field effect transistors.

Gas phase controlled deposition of high quality large-area graphene films.

A gas phase controlled graphene synthesis resembling a CVD process that does not critically depend on cooling rates is reported. The controllable catalytic CVD permits high quality large-area graphene formation with deft control over the thickness from monolayers to thick graphitic structures at temperatures as low as 750 degrees C.