Purely self-rectifying memristor-based passive crossbar array for artificial neural network accelerators.

Memristor-integrated passive crossbar arrays (CAs) could potentially accelerate neural network (NN) computations, but studies on these devices are limited to software-based simulations owing to their poor reliability. Herein, we propose a self-rectifying memristor-based 1 kb CA as a hardware accelerator for NN computations. We conducted fully hardware-based single-layer NN classification tasks involving the Modified National Institute of Standards and Technology database using the developed passive CA, and achieved 100% classification accuracy for 1500 test sets. We also investigated the influences of the defect-tolerance capability of the CA, impact of the conductance range of the integrated memristors, and presence or absence of selection functionality in the integrated memristors on the image classification tasks. We offer valuable insights into the behavior and performance of CA devices under various conditions and provide evidence of the practicality of memristor-integrated passive CAs as hardware accelerators for NN applications.

Direct Growth of Bi2SeO5 Thin Films for High-k Dielectrics via Atomic Layer Deposition.

This study describes a modified atomic layer deposition (ALD) process for fabricating BiOxSey thin films, targeting their application as high-k dielectrics in semiconductor devices, especially for two-dimensional semiconductors. Using an intermediate-enhanced ALD technique for Bi2Se3 and a plasma-enhanced ALD process for Bi2O3, a method for the sequential deposition of Bi2SeO5 ternary films has been established. The thin film has been deposited on SiO2 and TiN substrates, exhibiting growth rates of 0.17 to 0.16 nm·cycle-1 without an incubation period, thanks to facile nucleation characteristics. The resulting film exhibited high flatness and reached 96% of its theoretical density, forming a uniform nanocrystalline structure. Electrical evaluations using metal-insulator-metal capacitors indicated the dielectric constant (∼17.6) and electrical breakdown strength (2.6 MV·cm-1), demonstrating their potential as a dielectric layer.

Self-rectifying resistive memory in passive crossbar arrays.

Conventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf0.8Si0.2O2/Al2O3/Hf0.5Si0.5O2)-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 104), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 µs), (v) excellent non-volatility (data retention >104 s at 85 °C), and (vi) complementary metal-oxide-semiconductor compatibility (maximum supply voltage ≤5 V) is introduced, which outperforms previously reported SRMCs. These characteristics render the SRMC highly suitable for the main memory for memory-centric computing which can improve deep learning acceleration. Furthermore, the low programming power (ca. 18 nW), latency (100 µs), and endurance (>106) highlight the energy-efficiency and highly reliable random-access memory of our SRMC. The feasible operation of individual SRMCs in passive crossbar arrays of different sizes (30 × 30, 160 × 160, and 320 × 320) is attributed to the large asymmetry and nonlinearity in the current-voltage behavior of the proposed SRMC, verifying its potential for application in large-scale and high-density non-volatile memory for memory-centric computing.

Fully "Erase-free" Multi-Bit Operation in HfO2-Based Resistive Switching Device.

Fully "Erase-free" multi-bit operation was demonstrated in a W/HfO2/TiN-stacked resistive switching device. The term Erase-free means that a digital state in a multi-bit operation can be achieved without initializing the device resistance state when the device moves to another digital state. Because initializing the resistance state of a resistive switching device causes high energy consumption, omitting this sequence can achieve energy efficient multi-bit operation during rewriting of the resistance state of the device. Experimentally, an operational energy savings of up to 75% was confirmed. For stable and reliable Erase-free operation, several prerequisites are required, such as gradual resistance change with electric pulse stimuli during both writing and erasing, predictable operational voltages for certain resistance states, and high reliability of resistive switching. These prerequisites could be achieved by adopting a W top electrode in a W/HfO2/TiN-stacked resistive switching device. These results can pave the way to future nonvolatile memory applications.