Reconfigurable aJ-Level Ferroelectric Transistor-Based Boolean Logic for Logic-in-Memory.

Logic-in-memory (LIM) architecture holds great potential to break the von Neumann bottleneck. Despite the extensive research on novel devices, challenges persist in developing suitable engineering building blocks for such designs. Herein, we propose a reconfigurable strategy for efficient implementation of Boolean logics based on a hafnium oxide-based ferroelectric field effect transistor (HfO2-based FeFET). The logic results are stored within the device itself (in situ) during the computation process, featuring the key characteristics of LIM. The fast switching speed and low power consumption of a HfO2-based FeFET enable the execution of Boolean logics with an ultralow energy of lower than 8 attojoule (aJ). This represents a significant milestone in achieving aJ-level computing energy consumption. Furthermore, the system demonstrates exceptional reliability with computing endurance exceeding 108 cycles and retention properties exceeding 1000 s. These results highlight the remarkable potential of a FeFET for the realization of high performance beyond the von Neumann LIM computing architectures.

Reconfigurable Logic-in-Memory Computing Based on a Polarity-Controllable Two-Dimensional Transistor.

Logic-in-memory architecture holds great promise to meet the high-performance and energy-efficient requirements of data-intensive scenarios. Two-dimensional compacted transistors embedded with logic functions are expected to extend Moore's law toward advanced nodes. Here we demonstrate that a WSe2/h-BN/graphene based middle-floating-gate field-effect transistor can perform under diverse current levels due to the controllable polarity by the control gate, floating gate, and drain voltages. Such electrical tunable characteristics are employed for logic-in-memory architectures and can behave as reconfigurable logic functions of AND/XNOR within a single device. Compared to the conventional devices like floating-gate field-effect transistors, our design can greatly decrease the consumption of transistors. For AND/NAND, it can save 75% transistors by reducing the transistor number from 4 to 1; for XNOR/XOR, it is even up to 87.5% with the number being reduced from 8 to 1.

Optically Controllable Organic Logic-in-Memory: An Innovative Approach toward Ternary Data Processing and Storage.

Logic-in-memory (LIM) has emerged as an energy-efficient computing technology, as it integrates logic and memory operations in a single device architecture. Herein, a concept of ternary LIM is established. First, a p-type 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) transistor is combined with an n-type PhC2H4-benzo[de]isoquinolino[1,8-gh]quinolone diimide (PhC2-BQQDI) transistor to obtain a binary memory inverter, in which a zinc phthalocyanine-cored polystyrene (ZnPc-PS4) layer serves as a floating gate. The contrasting photoresponse of the transistors toward visible and ultraviolet light and the efficient hole-trapping ability of ZnPc-PS4 enable us to achieve an optically controllable memory operation with a high memory window of 18 V. Then, a ternary memory inverter is developed using an anti-ambipolar transistor to achieve a three-level data processing and storage system for more advanced LIM applications. Finally, low-voltage operation of the devices is achieved by employing a high-k dielectric layer, which highlights the potential of the developed LIM units for next-generation low-power electronics.

Reconfigurable Logic-in-Memory Constructed Using an Organic Antiambipolar Transistor.

We demonstrate an electrically reconfigurable two-input logic-in-memory (LIM) using a dual-gate-type organic antiambipolar transistor (DG-OAAT). The attractive feature of this device is that a phthalocyanine-cored star-shaped polystyrene is used as a nano-floating gate, which enables the electrical switching of individual logic circuits and stores the circuit information by the nonvolatile memory effect. First, the DG-OAAT exhibited Λ-shaped transfer curves with hysteresis by sweeping the bottom-gate voltage. Programming and erasing operations enabled the reversible shift of the Λ-shaped transfer curves. Furthermore, the top-gate voltage effectively tuned the peak voltages of the transfer curves. Consequently, the combination of dual-gate and memory effects achieved electrically reconfigurable two-input LIM operations. Individual logic circuits (e.g., OR/NAND, XOR/NOR, and AND/XOR) were reconfigured by the corresponding programming and erasing operations without any variations in the input signals. Our device concept has the potential to fulfill an epoch-making organic integration circuit with a simple device configuration.

Switchable Polar Nanotexture in Nanolaminates HfO2 -ZrO2 for Ultrafast Logic-in-Memory Operations.

Nontrivial topological polar textures in ferroelectric materials, including vortices, skyrmions, and others, have the potential to develop ultrafast, high-density, reliable multilevel memory storage and conceptually innovative processing units, even beyond the limit of binary storage of 180° aligned polar materials. However, the realization of switchable polar textures at room temperature in ferroelectric materials integrated directly into silicon using a straightforward large area fabrication technique and effectively utilizing it to design multilevel programable memory and processing units has not yet been demonstrated. Here, utilizing vector piezoresponse force and conductive atomic force microscopy, microscopic evidence of the electric field switchable polar nanotexture is provided at room temperature in HfO2 -ZrO2 nanolaminates grown directly onto silicon using an atomic layer deposition technique. Additionally, a two-terminal Au/nanolaminates/Si ferroelectric tunnel junction is designed, which shows ultrafast (≈83 ns) nonvolatile multilevel current switching with high on/off ratio (>106 ), long-term durability (>4000 s), and giant tunnel electroresistance (108 %). Furthermore, 14 Boolean logic operations are tested utilizing a single device as a proof-of-concept for reconfigurable logic-in-memory processing. The results offer a potential approach to "processing with polar textures" and addressing the challenges of developing high-performance multilevel in-memory processing technology by virtue of its fundamentally distinct mechanism of operation.

A van der Waals Integrated Damage-Free Memristor Based on Layered 2D Hexagonal Boron Nitride.

2D materials with intriguing properties have been widely used in optoelectronics. However, electronic devices suffered from structural damage due to the ultrathin materials and uncontrolled defects at interfaces upon metallization, which hindered the development of reliable devices. Here, a damage-free Au/h-BN/Au memristor is reported using a clean, water-assisted metal transfer approach by physically assembling Au electrodes onto the layered h-BN which minimized the structural damage and undesired interfacial defects. The memristors demonstrate significantly improved performance with the coexistence of nonpolar and threshold switching as well as tunable current levels by controlling the compliance current, compared with devices with evaporated contacts. The devices integrated into an array show suppressed sneak path current and can work as both logic gates and latches to implement logic operations allowing in-memory computing. Cross-sectional scanning transmission electron microscopy analysis validates the feasibility of this nondestructive metal integration approach, the crucial role of high-quality atomically sharp interface in resistive switching, and a direct observation of percolation path. The underlying mechanism of boron vacancies-assisted transport is further supported experimentally by conductive atomic force microscopy free from process-induced damage, and theoretically by ab initio simulations.

Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

Robust DNA-Bridged Memristor for Textile Chips.

Electronic textiles may revolutionize many fields, such as communication, health care and artificial intelligence. To date, unfortunately, computing with them is not yet possible. Memristors are compatible with the interwoven structure and manufacturing process in textiles because of its two-terminal crossbar configuration. However, it remains a challenge to realize textile memristors owing to the difficulties in designing advanced memristive materials and achieving high-quality active layers on fiber electrodes. Herein we report a robust textile memristor based on an electrophoretic-deposited active layer of deoxyribonucleic acid (DNA) on fiber electrodes. The unique architecture and orientation of DNA molecules with the incorporation of Ag nanoparticles offer the best-in-class performances, e.g., both ultra-low operation voltage of 0.3 V and power consumption of 100 pW and high switching speed of 20 ns. Fundamental logic calculations such as implication and NAND are demonstrated as functions of textile chips, and it has been thus integrated with power-supplying and light emitting modules to demonstrate an all-fabric information processing system.

Optically driven intelligent computing with ZnO memristor.

Artificial vision is crucial for most artificial intelligence applications. Conventional artificial visual systems have been facing challenges in terms of real-time information processing due to the physical separation of sensors, memories, and processors, which results in the production of a large amount of redundant data as well as the data conversion and transfer between these three components consuming most of the time and energy. Emergent optoelectronic memristors with the ability to realize integrated sensing-computing-memory (ISCM) are key candidates for solving such challenges and therefore attract increasing attention. At present, the memristive ISCM devices can only perform primary-level computing with external light signals due to the fact that only monotonic increase of memconductance upon light irradiation is achieved in most of these devices. Here, we propose an all-optically controlled memristive ISCM device based on a simple structure of Au/ZnO/Pt with the ZnO thin film sputtered at pure Ar atmosphere. This device can perform advanced computing tasks such as nonvolatile neuromorphic computing and complete Boolean logic functions only by light irradiation, owing to its ability to reversibly tune the memconductance with light. Moreover, the device shows excellent operation stability ascribed to a purely electronic memconductance tuning mechanism. Hence, this study is an important step towards the next generation of artificial visual systems.

Two-Dimensional Tunneling Memtransistor with Thin-Film Heterostructure for Low-Power Logic-in-Memory Complementary Metal-Oxide Semiconductor.

With the demand for high-performance and miniaturized semiconductor devices continuously rising, the development of innovative tunneling transistors via efficient stacking methods using two-dimensional (2D) building blocks has paramount importance in the electronic industry. Hence, 2D semiconductors with atomically thin geometries hold significant promise for advancements in electronics. In this study, we introduced tunneling memtransistors with a thin-film heterostructure composed of 2D semiconducting MoS2 and WSe2. Devices with the dual function of tuning and memory operation were realized by the gate-regulated modulation of the barrier height at the heterojunction and manipulation of intrinsic defects within the exfoliated nanoflakes using solution processes. Further, our investigation revealed extensive edge defects and four distinct defect types, namely monoselenium vacancies, diselenium vacancies, tungsten vacancies, and tungsten adatoms, in the interior of electrochemically exfoliated WSe2 nanoflakes. Additionally, we constructed complementary metal-oxide semiconductor-based logic-in-memory devices with a small static power in the range of picowatts using the developed tunneling memtransistors, demonstrating a promising approach for next-generation low-power nanoelectronics.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Graphene Oxide-Based Memristive Logic-in-Memory Circuit Enabling Normally-Off Computing.

Memristive logic-in-memory circuits can provide energy- and cost-efficient computing, which is essential for artificial intelligence-based applications in the coming Internet-of-things era. Although memristive logic-in-memory circuits have been previously reported, the logic architecture requiring additional components and the non-uniform switching of memristor have restricted demonstrations to simple gates. Using a nanoscale graphene oxide (GO) nanosheets-based memristor, we demonstrate the feasibility of a non-volatile logic-in-memory circuit that enables normally-off in-memory computing. The memristor based on GO film with an abundance of unusual functional groups exhibited unipolar resistive switching behavior with reliable endurance and retention characteristics, making it suitable for logic-in-memory circuit application. In a state of low resistance, temperature-dependent resistance and I-V characteristics indicated the presence of a metallic Ni filament. Using memristor-aided logic (MAGIC) architecture, we performed NOT and NOR gates experimentally. Additionally, other logic gates such as AND, NAND, and OR were successfully implemented by combining NOT and NOR universal logic gates in a crossbar array. These findings will pave the way for the development of next-generation computer systems beyond the von Neumann architecture, as well as carbon-based nanoelectronics in the future.

Controlling Isomerization of Photoswitches to Modulate 2D Logic-in-Memory Devices by Organic-Inorganic Interfacial Strategy.

Logic-in-memory devices are a promising and powerful approach to realize data processing and storage driven by electrical bias. Here, an innovative strategy is reported to achieve the multistage photomodulation of 2D logic-in-memory devices, which is realized by controlling the photoisomerization of donor-acceptor Stenhouse adducts (DASAs) on the surface of graphene. Alkyl chains with various carbon spacer lengths (n = 1, 5, 11, and 17) are introduced onto DASAs to optimize the organic-inorganic interfaces: 1) Prolonging the carbon spacers weakens the intermolecular aggregation and promotes isomerization in the solid state. 2) Too long alkyl chains induce crystallization on the surface and hinder the photoisomerization. Density functional theory calculation indicates that the photoisomerization of DASAs on the graphene surface is thermodynamically promoted by increasing the carbon spacer lengths. The 2D logic-in-memory devices are fabricated by assembling DASAs onto the surface. Green light irradiation increases the drain-source current (Ids ) of the devices, while heat triggers a reversed transfer. The multistage photomodulation is achieved by well-controlling the irradiation time and intensity. The strategy based on the dynamic control of 2D electronics by light integrates molecular programmability into the next generation of nanoelectronics.

Multifunctional Multigate One-Transistor with Thin Advanced Materials, Logic-in-Memory, and Artificial Synaptic Behaviors.

The high device density and fabrication complexity have hampered the development of the electronics. The advanced designs, which could implement the functions of the circuits with higher device density but less fabrication complexity, are hence required. Meanwhile, the MoS2-based devices have recently attracted considerable attention owing to their advantages such as the ultrathin thickness. However, the MoS2-based multifunctional multigate one-transistor (MGT) designs with logic-in-memory and artificial synaptic functions have rarely been reported. Here, an MGT structure based on the MoS2 channel is proposed, with both the logic-in-memory and artificial synaptic behaviors and with more controllable processes than the manual transfer. The proposed MoS2-based MGT functions could be attributed to the semijunction mechanism and enhanced effect of the additional terminals with improved controllability. This study is the first to demonstrate that the neuromorphic computing, logic gate, and memory functions can all be achieved in a MoS2 MGT device without using any additional layers or plasticity to a transistor. The reported results provide a new strategy for developing brain-like systems and next-generation electronics using multifunctional designs and ultrathin materials.

Reconfigurable and Efficient Implementation of 16 Boolean Logics and Full-Adder Functions with Memristor Crossbar for Beyond von Neumann In-Memory Computing.

The rise of emerging technologies such as Big Data, the Internet of Things, and artificial intelligence, which requires efficient power schemes, is driving brainstorming in data computing and storage technologies. In this study, merely relying on the fundamental structure of two memristors and a resistor, arbitrary Boolean logic can be reconfigured and calculated in two steps, while no additional voltage sources are needed beyond "±VP " and 0, and all state reversals are based on memristor set switching. Utilizing the proposed logic scheme in an elegant form of unity structure and minimum cost, the implementation of a 1-bit adder is demonstrated economically, and a promising circuit scheme for the N-bit adder is exhibited. Some critical issues including the crosstalk problem, energy consumption, and peripheral circuits are further simulated and discussed. Compared with existing works on memristive logic, such methods support building a memristor-based digital in-memory calculation system with high functional reconfigurability, simple voltage sources, and low power and area consumption.

Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing.

In-memory computing featuring a radical departure from the von Neumann architecture is promising to substantially reduce the energy and time consumption for data-intensive computation. With the increasing challenges facing silicon complementary metal-oxide-semiconductor (CMOS) technology, developing in-memory computing hardware would require a different platform to deliver significantly enhanced functionalities at the material and device level. Here, we explore a dual-gate two-dimensional ferroelectric field-effect transistor (2D FeFET) as a basic device to form both nonvolatile logic gates and artificial synapses, addressing in-memory computing simultaneously in digital and analog spaces. Through diversifying the electrostatic behaviors in 2D transistors with the dual-ferroelectric-coupling effect, rich logic functionalities including linear (AND, OR) and nonlinear (XNOR) gates were obtained in unipolar (MoS2) and ambipolar (MoTe2) FeFETs. Combining both types of 2D FeFETs in a heterogeneous platform, an important computation circuit, i.e., a half-adder, was successfully constructed with an area-efficient two-transistor structure. Furthermore, with the same device structure, several key synaptic functions are shown at the device level, and an artificial neural network is simulated at the system level, manifesting its potential for neuromorphic computing. These findings highlight the prospects of dual-gate 2D FeFETs for the development of multifunctional in-memory computing hardware capable of both digital and analog computation.

Anomalous Thermal-Assisted Spin-Orbit Torque-Induced Magnetization Switching for Energy-Efficient Logic-in-Memory.

Spin-orbit torque (SOT) is widely considered as an effective route to manipulate magnetic order in spintronic devices. The low power consumption and long endurance demands from future computer architectures urgently require a reduction of the critical SOT switching current density, jsw. However, except for searching for a SOT source with a high-spin Hall angle, few efficient mechanisms to reduce jsw have been proposed. In this work, we achieved an anomalous thermal-assisted (TA) jsw reduction in a Pt/Co/Tb heterostructure through engineering a ferrimagnetic Co/Tb interface. This jsw reduction tendency is demonstrated to be strongly dependent on the thickness of Tb, tTb. When tTb reaches an optimal point (3 nm), a 74 K temperature increase will reduce jsw by more than an order of magnitude (17 times). Comparison experiments and theoretical simulations indicate that this anomalous TA reduction behavior goes beyond the conventional SOT framework and originates from the temperature-sensitive ferrimagnetic interface. We further propose a multifunctional logic-in-memory device, where six different Boolean logic gates can be implemented, to demonstrate the application potential and energy efficiency of this TA SOT switching mechanism. Our work provides an effective alternative to reduce jsw in SOT devices and may inspire future spintronic memory, logic, and high-frequency devices.

Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor.

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic '1' to '0' and 7.9 (V/V) when transitioning from logic '0' to '1', while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption.

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing.

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

Light-Programmable Logic-in-Memory in 2D Semiconductors Enabled by Supramolecular Functionalization: Photoresponsive Collective Effect of Aligned Molecular Dipoles.

Nowadays, the unrelenting growth of the digital universe calls for radically novel strategies for data processing and storage. An extremely promising and powerful approach relies on the development of logic-in-memory (LiM) devices through the use of floating gate and ferroelectric technologies to write and erase data in a memory operating as a logic gate driven by electrical bias. In this work, we report an alternative approach to realize the logic-in-memory based on two-dimensional (2D) transition metal dichalcogenides (TMDs) where multiple memorized logic output states have been established via the interface with responsive molecular dipoles arranged in supramolecular arrays. The collective dynamic molecular dipole changes of the axial ligand coordinated onto self-assembled metal phthalocyanine nanostructures on the surface of 2D TMD enables large reversible modulation of the Fermi level of both n-type molybdenum disulfide (MoS2) and p-type tungsten diselenide (WSe2) field-effect transistors (FETs), to achieve multiple memory states by programming and erasing with ultraviolet (UV) and with visible light, respectively. As a result, logic-in-memory devices were built up with our supramolecular layer/2D TMD architecture where the output logic is encoded by the motion of the molecular dipoles. Our strategy relying on the dynamic control of the 2D electronics by harnessing the functions of molecular-dipole-induced memory in a supramolecular hybrid layer represents a versatile way to integrate the functional programmability of molecular science into the next generation nanoelectronics.