A Real-Time Affective Computing Platform Integrated with AI System-on-Chip Design and Multimodal Signal Processing System.

Recently, deep learning algorithms have been used widely in emotion recognition applications. However, it is difficult to detect human emotions in real-time due to constraints imposed by computing power and convergence latency. This paper proposes a real-time affective computing platform that integrates an AI System-on-Chip (SoC) design and multimodal signal processing systems composed of electroencephalogram (EEG), electrocardiogram (ECG), and photoplethysmogram (PPG) signals. To extract the emotional features of the EEG, ECG, and PPG signals, we used a short-time Fourier transform (STFT) for the EEG signal and direct extraction using the raw signals for the ECG and PPG signals. The long-term recurrent convolution networks (LRCN) classifier was implemented in an AI SoC design and divided emotions into three classes: happy, angry, and sad. The proposed LRCN classifier reached an average accuracy of 77.41% for cross-subject validation. The platform consists of wearable physiological sensors and multimodal signal processors integrated with the LRCN SoC design. The area of the core and total power consumption of the LRCN chip was 1.13 x 1.14 mm2 and 48.24 mW, respectively. The on-chip training processing time and real-time classification processing time are 5.5 µs and 1.9 µs per sample. The proposed platform displays the classification results of emotion calculation on the graphical user interface (GUI) every one second for real-time emotion monitoring.Clinical relevance- The on-chip training processing time and real-time emotion classification processing time are 5.5 µs and 1.9 µs per sample with EEG, ECG, and PPG signal based on the LRCN model.

A SOC Design of ORICA-based Highly Effective Real-time Multi-channel EEG System.

Independent component analysis (ICA) has been wildly used to improve EEG based application such as brain computer interface (BCI). However, some well know ICA algorithm, such as Infomax ICA, suffering from the problem of convergence latency and make it hard to be apply on real-time application. This paper proposes a highly efficient chip implementation of multi-channel EEG real-time system based on online recursive independent component analysis algorithm (ORICA). The core size of the chip is 1.5525-mm2 using 28nm CMOS technology. The EEG demonstration board will be implemented with the ORICA chip. The operation frequency and power consumption of the chip are 100 MHz and 17.9 mW respectively. The proposed chip was validated with a real-time circuit integrated system and the average correlation coefficient between simulations results and chip processing results is 0.958.

A SOC Design of ORICA-based Highly Effective Real-time Multi-channel EEG System.

Independent component analysis (ICA) has been wildly used to improve EEG based application such as brain computer interface (BCI). However, some well know ICA algorithm, such as Infomax ICA, suffering from the problem of convergence latency and make it hard to be apply on real-time application. This paper proposes a highly efficient chip implementation of multi-channel EEG real-time system based on online recursive independent component analysis algorithm (ORICA). The core size of the chip is 1.5525-mm2 using 28nm CMOS technology. The EEG demonstration board will be implemented with the ORICA chip. The operation frequency and power consumption of the chip are 100 MHz and 17.9 mW respectively. The proposed chip was validated with a real-time circuit integrated system and the average correlation coefficient between simulations results and chip processing results is 0.958.

A Wearable Channel Selection-Based Brain-Computer Interface for Motor Imagery Detection.

Motor imagery-based brain-computer interface (BCI) is a communication interface between an external machine and the brain. Many kinds of spatial filters are used in BCIs to enhance the electroencephalography (EEG) features related to motor imagery. The approach of channel selection, developed to reserve meaningful EEG channels, is also an important technique for the development of BCIs. However, current BCI systems require a conventional EEG machine and EEG electrodes with conductive gel to acquire multi-channel EEG signals and then transmit these EEG signals to the back-end computer to perform the approach of channel selection. This reduces the convenience of use in daily life and increases the limitations of BCI applications. In order to improve the above issues, a novel wearable channel selection-based brain-computer interface is proposed. Here, retractable comb-shaped active dry electrodes are designed to measure the EEG signals on a hairy site, without conductive gel. By the design of analog CAR spatial filters and the firmware of EEG acquisition module, the function of spatial filters could be performed without any calculation, and channel selection could be performed in the front-end device to improve the practicability of detecting motor imagery in the wearable EEG device directly or in commercial mobile phones or tablets, which may have relatively low system specifications. Finally, the performance of the proposed BCI is investigated, and the experimental results show that the proposed system is a good wearable BCI system prototype.

Wireless Monitoring System for Oral-Feeding Evaluation of Preterm Infants.

The oral feeding disorder is one of the important indicators for the high risk group of neurodevelopment delay. The procedure of oral feeding requires the coordination of sucking, swallowing, and breathing activities, and it is the most complex sensorimotor process for newborn infants. Premature infants often uneasily complete the procedure of oral feeding. However, the evaluation of the oral feeding disorders and severity are usually dependent on the subjective clinical experience of the physician. Monitoring the sucking-swallowing-breathing activities directly is difficult for preterm infants. In this study, a wireless monitoring system for oral-feeding evaluation of full term and preterm infants was proposed to objectively and quantitatively evaluate the coordination of suck-swallow-respiration function during oral feeding. Moreover, the ratios of the swallowing and breathing event numbers to the sucking event number were defined to evaluate the coordination of suck-swallow-respiration function during oral feeding. Finally, the system performance was validated and the coordination of suck-swallow-respiration function for full term and preterm infants during oral feeding was also investigated.

Real-time obstructive sleep apnea detection from frequency analysis of EDR and HRV using Lomb Periodogram.

In this study, an effective real-time obstructive sleep apnea (OSA) detection method from frequency analysis of ECG-derived respiratory (EDR) and heart rate variability (HRV) is proposed. Compared to traditional Polysomnography (PSG) which needs several physiological signals measured from patients, the proposed OSA detection method just only use ECG signals to determine the time interval of OSA. In order to be feasible to be implemented in hardware to achieve the real-time detection and portable application, the simplified Lomb Periodogram is utilized to perform the frequency analysis of EDR and HRV in this study. The experimental results of this work indicate that the overall accuracy can be effectively increased with values of Specificity (Sp) of 91%, Sensitivity (Se) of 95.7%, and Accuracy of 93.2% by integrating the EDR and HRV indexes.

A non-linear iterative method for multi-layer DOT sub-surface imaging system.

Diffuse Optical Tomography (DOT) has become an emerging non-invasive technology, and has been widely used in clinical diagnosis. Functional near-infrared (FNIR) is one of the important applications of DOT. However, FNIR is used to reconstruct two-dimensional (2D) images for the sake of good spatial and temporal resolution. In this paper we propose a multiple-input and multiple-output (MIMO) based data extraction algorithm method in order to increase the spatial and temporal resolution. The non-linear iterative method is used to reconstruct better resolution images layer by layer. In terms of theory, the simulation results and original images are nearly identical. The proposed reconstruction method performs good spatial resolution, and has a depth resolutions capacity of three layers.

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763.

Authenticity preservation with histogram-based reversible data hiding and quadtree concepts.

With the widespread use of identification systems, establishing authenticity with sensors has become an important research issue. Among the schemes for making authenticity verification based on information security possible, reversible data hiding has attracted much attention during the past few years. With its characteristics of reversibility, the scheme is required to fulfill the goals from two aspects. On the one hand, at the encoder, the secret information needs to be embedded into the original image by some algorithms, such that the output image will resemble the input one as much as possible. On the other hand, at the decoder, both the secret information and the original image must be correctly extracted and recovered, and they should be identical to their embedding counterparts. Under the requirement of reversibility, for evaluating the performance of the data hiding algorithm, the output image quality, named imperceptibility, and the number of bits for embedding, called capacity, are the two key factors to access the effectiveness of the algorithm. Besides, the size of side information for making decoding possible should also be evaluated. Here we consider using the characteristics of original images for developing our method with better performance. In this paper, we propose an algorithm that has the ability to provide more capacity than conventional algorithms, with similar output image quality after embedding, and comparable side information produced. Simulation results demonstrate the applicability and better performance of our algorithm.

Bio-inspired microsystem for robust genetic assay recognition.

A compact integrated system-on-chip (SoC) architecture solution for robust, real-time, and on-site genetic analysis has been proposed. This microsystem solution is noise-tolerable and suitable for analyzing the weak fluorescence patterns from a PCR prepared dual-labeled DNA microchip assay. In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals. A posterior VLSI artificial neural network (ANN) processor chip is used for analyzing the processed signals from the differential logarithm stage. A single-channel logarithmic circuit was fabricated and characterized. A prototype ANN chip with unsupervised winner-take-all (WTA) function was designed, fabricated, and tested. An ANN learning algorithm using a novel sigmoid-logarithmic transfer function based on the supervised backpropagation (BP) algorithm is proposed for robustly recognizing low-intensity patterns. Our results show that the trained new ANN can recognize low-fluorescence patterns better than an ANN using the conventional sigmoid function.