Drift of Schottky Barrier Height in Phase Change Materials.

Phase-change memory (PCM) devices have great potential as multilevel memory cells and artificial synapses for neuromorphic computing hardware. However, their practical use is hampered by resistance drift, a phenomenon commonly attributed to structural relaxation or electronic mechanisms primarily in the context of bulk effects. In this study, we reevaluate the electrical manifestation of resistance drift in sub-100 nm Ge2Sb2Te5 (GST) PCM devices, focusing on the contributions of bulk vs interface effects. We employ a combination of measurement techniques to elucidate the current transport mechanism and the electrical manifestation of resistance drift. Our steady-state temperature-dependent measurements reveal that resistance in these devices is predominantly influenced by their electrical contacts, with conduction occurring through thermionic emission (Schottky) at the contacts. Additionally, temporal current-voltage characterization allows us to link the resistance drift to a time-dependent increase in the Schottky barrier height. These findings provide valuable insights, pinpointing the primary contributor to resistance drift in PCM devices: the Schottky barrier height for hole injection at the interface. This underscores the significance of contacts (interface) in the electrical manifestation of drift in PCM devices.

A Sub-Micron Spherical Atomic Force Microscopic Tip for Surface Measurements.

We report a novel methodology for fabricating a sub-micron spherical atomic force microscope (AFM) tip controllably-a silicon sub-micron sphere atop microcantilevers, which is desired for precise nanoscale tribology measurements, biological studies, and colloid science. Silicon sub-micron spheres are fabricated through swelling of single-crystal silicon with proper high-energy helium ion dosing, a traditionally undesired phenomenon known in helium ion microscopy. Silicon sub-micron spheres with diameters from 100 nm to 1 µm are demonstrated, and the placement of silicon sub-micron spheres can be as accurate as 10 nm or even below. This AFM tip demonstrates robust measurements during friction tests on graphene/silicon oxide substrates for more than 10 000 cycles. This AFM tip overcomes a critical challenge of reducing the size of spherical AFM tips from the micrometer scale to the sub-micron scale and is promising in cross-scale mechanics studies, nanotribology, colloid science, and biology.

Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

Intrinsically ultrastrong plasmon-exciton interactions in crystallized films of carbon nanotubes.

In cavity quantum electrodynamics, optical emitters that are strongly coupled to cavities give rise to polaritons with characteristics of both the emitters and the cavity excitations. We show that carbon nanotubes can be crystallized into chip-scale, two-dimensionally ordered films and that this material enables intrinsically ultrastrong emitter-cavity interactions: Rather than interacting with external cavities, nanotube excitons couple to the near-infrared plasmon resonances of the nanotubes themselves. Our polycrystalline nanotube films have a hexagonal crystal structure, ∼25-nm domains, and a 1.74-nm lattice constant. With this extremely high nanotube density and nearly ideal plasmon-exciton spatial overlap, plasmon-exciton coupling strengths reach 0.5 eV, which is 75% of the bare exciton energy and a near record for room-temperature ultrastrong coupling. Crystallized nanotube films represent a milestone in nanomaterials assembly and provide a compelling foundation for high-ampacity conductors, low-power optical switches, and tunable optical antennas.

Directed Self-Assembly of Ge Quantum Dots Using Focused Si2+ Ion Beam Patterning.

We show that templating a Si surface with a focused beam of Si2+ or Si+ ions can create suitable nucleation sites for the subsequent growth of self-assembled Ge quantum dots by chemical vapor deposition. To determine the mechanism of patterning we use atomic force microscopy to show that, similar to Ga+ patterning, the formation of a surface pit is required to enable control over Ge quantum dot locations. We find that relatively high implantation doses are required to achieve patterning, and these doses lead to amorphization of the substrate. We assess the degree to which the substrate crystallinity can be recovered by subsequent processing. Using in situ transmission electron microscopy heating experiments we find that recrystallization is possible at the growth temperature of the Ge quantum dots, but defects remain that follow the pattern of the initial implantation. We discuss the formation mechanism of the defects and the benefits of using Si ions for patterning both defects and quantum dots on Si substrates.

Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules.

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

First realization of the piezoelectronic stress-based transduction device.

We present the first realization of a monolithically integrated piezoelectronic transistor (PET), a new transduction-based computer switch which could potentially operate conventional computer logic at 1/50 the power requirements of current Si-based transistors (Chen 2014 Proc. IEEE ICICDT pp 1-4; Mamaluy et al 2014 Proc. IWCE pp 1-2). In PET operation, an input gate voltage expands a piezoelectric element (PE), transducing the input into a pressure pulse which compresses a piezoresistive element (PR). The PR resistance goes down, transducing the signal back to voltage and turning the switch 'on'. This transduction physics, in principle, allows fast, low-voltage operation. In this work, we address the processing challenges of integrating chemically incompatible PR and PE materials together within a surrounding cage against which the PR can be compressed. This proof-of-concept demonstration of a fully integrated, stand-alone PET device is a key step in the development path toward a fast, low-power very large scale integration technology.

Vertical III-V nanowire device integration on Si(100).

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices.

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

Carbon nanotube complementary wrap-gate transistors.

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

Sub-10 nm carbon nanotube transistor.

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/µm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade-nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.

Multiple double cross-section transmission electron microscope sample preparation of specific sub-10 nm diameter Si nanowire devices.

The ability to prepare multiple cross-section transmission electron microscope (XTEM) samples from one XTEM sample of specific sub-10 nm features was demonstrated. Sub-10 nm diameter Si nanowire (NW) devices were initially cross-sectioned using a dual-beam focused ion beam system in a direction running parallel to the device channel. From this XTEM sample, both low- and high-resolution transmission electron microscope (TEM) images were obtained from six separate, specific site Si NW devices. The XTEM sample was then re-sectioned in four separate locations in a direction perpendicular to the device channel: 90° from the original XTEM sample direction. Three of the four XTEM samples were successfully sectioned in the gate region of the device. From these three samples, low- and high-resolution TEM images of the Si NW were taken and measurements of the NW diameters were obtained. This technique demonstrated the ability to obtain high-resolution TEM images in directions 90° from one another of multiple, specific sub-10 nm features that were spaced 1.1 µm apart.

Three-dimensional measurement of line edge roughness in copper wires using electron tomography.

Electrical interconnects in integrated circuits have shrunk to sizes in the range of 20-100 nm. Accurate measurements of the dimensions of these nanowires are essential for identifying the dominant electron scattering mechanisms affecting wire resistivity as they continue to shrink. We report a systematic study of the effect of line edge roughness on the apparent cross-sectional area of 90 nm Cu wires with a TaN/Ta barrier measured by conventional two-dimensional projection imaging and three-dimensional electron tomography. Discrepancies in area measurements due to the overlap of defects along the wire's length lead to a 5% difference in the resistivities predicted by the two methods. Tomography of thick cross sections is shown to give a more accurate representation of the original structure and allows more efficient sampling of the wire's cross-sectional area. The effect of roughness on measurements from projection images is minimized for cross-section thicknesses less than 50 nm, or approximately half the spatial frequency of the roughness variations along the length of the investigated wires.

Tungsten oxide nanowire growth by chemically induced strain.

We have investigated the formation of tungsten oxide nanowires under different chemical vapor deposition (CVD) conditions. We find that exposure of oxidized tungsten films to hydrogen and methane at 900 degrees C leads to the formation of a dense array of typically 10 nm diameter nanowires. Structural and chemical analysis shows that the wires are crystalline WO3. We propose a chemically driven whisker growth mechanism in which interfacial strain associated with the formation of tungsten carbide stimulates nanowire growth. This might be a general concept, applicable also to other nanowire systems.