Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD.

In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V3D3)) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V3D3) was integrated in high aspect ratio TSV (10 × 100 µm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.

Effect of Silane Monolayers and Nanoporous Silicon Surfaces on the Matrix-Assisted Laser Desorption Ionization Mass Spectrometry Detection of Sepsis Metabolites Biomarkers Mixed in Solution.

Matrix-assisted laser desorption ionization time-of-flight mass spectrometry (MALDI-ToF MS) is a promising strategy for clinical diagnosis based on metabolite detection. However, several bottlenecks (such as the lack of reproducibility in analysis, the presence of an important background in low-mass range, and the lack of organic matrix for some molecules) prevent its transfer to clinical cases. These limitations can be addressed by using nanoporous silicon surfaces chemically functionalized with silane monolayers. In the present study, sepsis metabolite biomarkers were used to investigate the effects of silane monolayers and porous silicon substrates on MALDI-ToF MS analysis (signal-to-noise value (S/N), relative standard deviation of the S/N of triplicate samples (STDmean), and intra-substrates uniformity). Also, the impact of the physicochemical properties of metabolites, with different isoelectric points and hydrophobic-hydrophilic balances, was assessed. Four different silane molecules, with various alkyl chain lengths and head-group charges, were self-assembled in monolayers on plane and porous silicon surfaces. Their surface coverage and conformity were investigated by X-ray photoelectron spectroscopy (XPS) and time-of-flight secondary ion mass spectrometry (ToF-SIMS). The seven metabolites detected on the stainless-steel target plate (lysophosphatidylcholine, caffeine, phenylalanine, creatinine, valine, arginine, and glycerophosphocholine) are also detected on the silanized and bare, plane and porous silicon surfaces. Moreover, two metabolites, glycine and alanine, which are not detected on the stainless-steel target plate, are detected on all silanized surfaces, except glycine which is not detected on CH3 short-modified porous silicon and on the bare plane silicon substrate. In addition, whatever the metabolites (except phenylalanine and valine), at least one of the silicon surfaces allows to increase the S/N value in comparison with the stainless-steel target plate. Also, the heterogeneity of matrix crystallization features is linked to the STDmean which is poor on the NH3+ monolayer on plane substrate and better on the NH3+ monolayer on porous substrate, for most of the metabolites. Nevertheless, matrix crystallization features are not sufficient to systematically get high STDmean and uniformity in MALDI-ToF MS analysis. Indeed, the physicochemical properties of metabolites and surfaces, limitations in metabolite extraction from the pores, and improvement in metabolite desorption due to the pores are shown to significantly impact MS analysis. In particular, in the case of the most hydrophobic metabolites studied, the highest S/N values and the best STDmean and uniformity (the lowest values) are reached by using porous substrates, while in the case of the most hydrophilic metabolites studied, plane substrates demonstrated the highest S/N and the lowest STDmean. No clear trend of surface chemistry was evidenced.

Effects of Silane Monolayers on Lysophosphatidylcholine (LysoPC) Detection by Desorption Ionization on Silicon Mass Spectrometry (DIOS-MS) in Solution and Plasma.

Desorption ionization on silicon mass spectrometry (DIOS-MS) enables high throughput analysis of low-molecular-weight biomolecules. However, detection of metabolite biomarkers in complex fluids such as plasma requires sample pretreatment, limiting clinical application. Here, we show that porous silicon, chemically modified using monolayers of n-propyldimethylmethoxysilane molecules, is a good candidate for fingerprinting lysophosphatidylcholine (lysoPC) in plasma, without sample pretreatment, for DIOS-MS-based diagnosis (e.g., sepsis). Results were correlated to lysoPC molecule location inside/outside the pores, determined by time-of-flight secondary ion mass spectrometry profiling, and to physicochemical properties.

ZIF-8 thin films by a vapor-phase process: limits to growth.

Metal-organic frameworks are a class of porous materials that show promising properties in the field of microelectronics. To reach industrial use of these materials, gas phase techniques are often preferred and were recently introduced. However, the thicknesses achieved are not sufficient, limiting further development. In this work, an improved gas phase process allowing ZIF-8 layer formation of several hundreds of nm using cyclic ligand/water exposures is described. Then, by a combination of in-depth surface analyses and molecular dynamics simulations, the presence and role of hydroxyl defects in the ZIF-8 layer to reach this thickness are established. At the same time, this study unveils an inherent limit of the method: thickness growth is consubstantial with defect repairing upon the crystallites ripening; such defect repairing eventually leads to the decrease of the pore window below the diffusion radius of the incoming linker, thus apparently capping the maximum MOF thickness observable for this type of material topology through this growth method.

Filling of Nanometric Pores with Polymer by Initiated Chemical Vapor Deposition.

The integration of porous thin films using microelectronic compatible processes sometimes requires the protection of the interior of the pores during the critical integration steps. In this paper, the polymerization of neo-pentyl methacrylate (npMA) is performed via initiated chemical vapor deposition (iCVD) on a porous organosilicate (SiOCH) and on a dense SiOCH. The characterizations by Fourier-transform infrared spectroscopy, spectroscopic ellipsometry, and time-of-flight secondary ion mass spectrometry of the different stacks show that iCVD is a powerful technique to polymerize npMA in the nanometric pores and thus totally fill them with a polymer. The study of the pore filling for very short iCVD durations shows that the polymerization in the pores is complete in less than ten seconds and is uniform in depth. Then, the poly(npMA) film growth continues on top of the filled SiOCH layer. These characteristics make iCVD a straightforward and very promising alternative to other infiltration techniques in order to fill the porosity of microporous thin films.

Spin-coated and PECVD low dielectric constant porous organosilicate films studied by 1D and 2D solid-state NMR.

In the research field of the sub-65 nm semiconductor industry, organosilicate SiOCH films with low dielectric constant (k < 2.4) need to be developed in order to improve the performance of integrated circuits [International Roadmap for Semiconductors (ITRS), San Jose, CA, 2004]. One way to produce SiOCH films of low dielectric constant is to introduce pores into the film. This is usually obtained in two steps. Firstly, co-deposition of a matrix precursor, with a sacrificial organic porogen, either by plasma enhanced chemical vapor deposition (PECVD) or spin-coating. Secondly, application of a specific thermal treatment to remove the porogen and create the porosity. This last step can be improved by adding to the thermal process a super-critical CO(2) treatment, an UV irradiation or an electronic bombardment (e-beam). In this study, the two deposition processes as well as the various treatments applied to eliminate the porogens were evaluated and compared using high-resolution solid-state NMR. For this purpose, hybrid (containing porogens) and porous films were extensively characterized on the basis of their (1)H, (13)C and (29)Si high-resolution NMR spectra. Information was obtained concerning the crosslinking of the Si skeleton. Spectral features could be correlated to the processes used. Isotropic chemical shift analyses and 2D correlation NMR experiments were used to show the existence and nature of the interactions between the matrix precursor and the organic porogen.

Catalyst preparation for CMOS-compatible silicon nanowire synthesis.

Metallic contamination was key to the discovery of semiconductor nanowires, but today it stands in the way of their adoption by the semiconductor industry. This is because many of the metallic catalysts required for nanowire growth are not compatible with standard CMOS (complementary metal oxide semiconductor) fabrication processes. Nanowire synthesis with those metals that are CMOS compatible, such as aluminium and copper, necessitate temperatures higher than 450 degrees C, which is the maximum temperature allowed in CMOS processing. Here, we demonstrate that the synthesis temperature of silicon nanowires using copper-based catalysts is limited by catalyst preparation. We show that the appropriate catalyst can be produced by chemical means at temperatures as low as 400 degrees C. This is achieved by oxidizing the catalyst precursor, contradicting the accepted wisdom that oxygen prevents metal-catalysed nanowire growth. By simultaneously solving material compatibility and temperature issues, this catalyst synthesis could represent an important step towards real-world applications of semiconductor nanowires.