All van der Waals Semiconducting PtSe2 Field Effect Transistors with Low Contact Resistance Graphite Electrodes.

Contact resistance is a multifaceted challenge faced by the 2D materials community. Large Schottky barrier heights and gap-state pinning are active obstacles that require an integrated approach to achieve the development of high-performance electronic devices based on 2D materials. In this work, we present semiconducting PtSe2 field effect transistors with all-van-der-Waals electrode and dielectric interfaces. We use graphite contacts, which enable high ION/IOFF ratios up to 109 with currents above 100 µA µm-1 and mobilities of 50 cm2 V-1 s-1 at room temperature and over 400 cm2 V-1 s-1 at 10 K. The devices exhibit high stability with a maximum hysteresis width below 36 mV nm-1. The contact resistance at the graphite-PtSe2 interface is found to be below 700 Ω µm. Our results present PtSe2 as a promising candidate for the realization of high-performance 2D circuits built solely with 2D materials.

Observation of Rich Defect Dynamics in Monolayer MoS2.

Defects play a pivotal role in limiting the performance and reliability of nanoscale devices. Field-effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors such as monolayer MoS2 are no exception. Probing defect dynamics in 2D FETs is therefore of significant interest. Here, we present a comprehensive insight into various defect dynamics observed in monolayer MoS2 FETs at varying gate biases and temperatures. The measured source-to-drain currents exhibit random telegraph signals (RTS) owing to the transfer of charges between the semiconducting channel and individual defects. Based on the modeled temperature and gate bias dependence, oxygen vacancies or aluminum interstitials are probable defect candidates. Several types of RTSs are observed including anomalous RTS and giant RTS indicating local current crowding effects and rich defect dynamics in monolayer MoS2 FETs. This study explores defect dynamics in large area-grown monolayer MoS2 with ALD-grown Al2O3 as the gate dielectric.

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.

For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning.

Electronic devices based on two-dimensional semiconductors suffer from limited electrical stability because charge carriers originating from the semiconductors interact with defects in the surrounding insulators. In field-effect transistors, the resulting trapped charges can lead to large hysteresis and device drifts, particularly when common amorphous gate oxides (such as silicon or hafnium dioxide) are used, hindering stable circuit operation. Here, we show that device stability in graphene-based field-effect transistors with amorphous gate oxides can be improved by Fermi-level tuning. We deliberately tune the Fermi level of the channel to maximize the energy distance between the charge carriers in the channel and the defect bands in the amorphous aluminium gate oxide. Charge trapping is highly sensitive to the energetic alignment of the Fermi level of the channel with the defect band in the insulator, and thus, our approach minimizes the amount of electrically active border traps without the need to reduce the total number of traps in the insulator.

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time-zero and time-dependent variability in the performance of the transistors appear critical. While time-zero variability is primarily related to immature processing, time-dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time-dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor-related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

Insulators for 2D nanoelectronics: the gap to bridge.

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators.

Dielectric Properties of Ultrathin CaF2 Ionic Crystals.

Mechanically exfoliated 2D hexagonal boron nitride (h-BN) is currently the preferred dielectric material to interact with graphene and 2D transition metal dichalcogenides in nanoelectronic devices, as they form a clean van der Waals interface. However, h-BN has a low dielectric constant (≈3.9), which in ultrascaled devices results in high leakage current and premature dielectric breakdown. Furthermore, the synthesis of h-BN using scalable methods, such as chemical vapor deposition, requires very high temperatures (>900 °C) , and the resulting h-BN stacks contain abundant few-atoms-wide amorphous regions that decrease its homogeneity and dielectric strength. Here it is shown that ultrathin calcium fluoride (CaF2 ) ionic crystals could be an excellent solution to mitigate these problems. By applying >3000 ramped voltage stresses and several current maps at different locations of the samples via conductive atomic force microscopy, it is statistically demonstrated that ultrathin CaF2 shows much better dielectric performance (i.e., homogeneity, leakage current, and dielectric strength) than SiO2 , TiO2 , and h-BN. The main reason behind this behavior is that the cubic crystalline structure of CaF2 is continuous and free of defects over large regions, which prevents the formation of electrically weak spots.

Characterization of Single Defects in Ultrascaled MoS2 Field-Effect Transistors.

MoS2 has received a lot of attention lately as a semiconducting channel material for electronic devices, in part due to its large band gap as compared to that of other 2D materials. Yet, the performance and reliability of these devices are still severely limited by defects which act as traps for charge carriers, causing severely reduced mobilities, hysteresis, and long-term drift. Despite their importance, these defects are only poorly understood. One fundamental problem in defect characterization is that due to the large defect concentration only the average response to bias changes can be measured. On the basis of such averaged data, a detailed analysis of their properties and identification of particular defect types are difficult. To overcome this limitation, we here characterize single defects on MoS2 devices by performing measurements on ultrascaled transistors (∼65 × 50 nm) which contain only a few defects. These single defects are characterized electrically at varying gate biases and temperatures. The measured currents contain random telegraph noise, which is due to the transfer of charge between the channel of the transistors and individual defects, visible only due to the large impact of a single elementary charge on the local electrostatics in these small devices. Using hidden Markov models for statistical analysis, we extract the charge capture and emission times of a number of defects. By comparing the bias-dependence of the measured capture and emission times to the prediction of theoretical models, we provide simple rules to distinguish oxide traps from adsorbates on these back-gated devices. In addition, we give simple expressions to estimate the vertical and energetic positions of the defects. Using the methods presented in this work, it is possible to locate the sources of performance and reliability limitations in 2D devices and to probe defect distributions in oxide materials with 2D channel materials.