Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρC) and width-normalized contact resistance (RCW) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (tIGTO)-dependent electrical contact properties of IGZO TFT, where ρC and RCW decrease as tIGTO increases to 8 nm. However, at tIGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρC and RCW of 9.0 × 10-6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10-4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.
As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors (OSs) have gained tremendous attention to continue the ever-demanding downscaling represented by Moore's law. Among them, OS is considered to be the most promising alternative material because it has intriguing features such as modest mobility, extremely low off-current, great uniformity, and low-temperature processibility with conventional complementary-metal-oxide-semiconductor-compatible methods. In practice, OS has successfully replaced hydrogenated amorphous Si in high-end liquid crystal display devices and has now become a standard backplane electronic for organic light-emitting diode displays despite the short time since their invention in 2004. For OS to be implemented in next-generation electronics such as back-end-of-line transistor applications in monolithic 3D integration beyond the display applications, however, there is still much room for further study, such as high mobility, immune short-channel effects, low electrical contact properties, etc. This study reviews the brief history of OS and recent progress in device applications from a material science and device physics point of view. Simultaneously, remaining challenges and opportunities in OS for use in next-generation electronics are discussed.
Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary metal-oxide-semiconductor (CMOS) technology. The discovery of ferroelectricity in fluorite-structured oxides revived interest in the research on ferroelectric memories, by inducing nanoscale nonvolatility in state-of-the-art gate insulators by minute doping and thermal treatment. The potential of this approach has been demonstrated by the fabrication of sub-30 nm electronic devices. Nonetheless, to realize practical applications, various technical limitations, such as insufficient reliability including endurance, retention, and imprint, as well as large device-to-device-variation, require urgent solutions. Furthermore, such limitations should be considered based on targeting devices as well as applications. Various types of ferroelectric memories including ferroelectric random-access-memory, ferroelectric field-effect-transistor, and ferroelectric tunnel junction should be considered for classical nonvolatile memories as well as emerging neuromorphic computing and processing-in-memory. Therefore, from the viewpoint of materials science, this review covers the recent research focusing on ferroelectric memories from the history of conventional approaches to future prospects.
In this paper, the feasibility of an indium-gallium oxide (In2(1-x)Ga2xOy) film through combinatorial atomic layer deposition (ALD) as an alternative channel material for back-end-of-line (BEOL) compatible transistor applications is studied. The microstructure of random polycrystalline In2Oy with a bixbyite structure was converted to the amorphous phase of In2(1-x)Ga2xOy film under thermal annealing at 400 °C when the fraction of Ga is ≥29 at.â¯%. In contrast, the enhancement in the orientation of the (222) face and subsequent grain size was observed for the In1.60Ga0.40Oy film with the intermediate Ga fraction of 20 at.â¯%. The suitability as a channel layer was tested on the 10-nm-thick HfO2 gate oxide where the natural length was designed to meet the requirement of short channel devices with a smaller gate length (<100 nm). The In1.60Ga0.40Oy thin-film transistors (TFTs) exhibited the high field-effect mobility (µFE) of 71.27 ± 0.98 cm2/(V s), low subthreshold gate swing (SS) of 74.4 mV/decade, threshold voltage (VTH) of -0.3 V, and ION/OFF ratio of >108, which would be applicable to the logic devices such as peripheral circuit of heterogeneous DRAM. The in-depth origin for this promising performance was discussed in detail, based on physical, optical, and chemical analysis.
In this Letter, we report Ge p-i-n avalanche photodetectors (APD) with low dark current (sub 1 µA below V(R)=5 V), low operating voltage (avalanche breakdown voltage=8-13 V), and high multiplication gain (440-680) by exploiting a point defect healing method (between 600°C and 650°C) and optimizing the doping concentration of the intrinsic region (p-type ~10¹7 cm⻳). In addition, Raman spectroscopy and electrochemical capacitance voltage analyses were performed to investigate the junction interfaces in more detail. This successful demonstration of Ge p-i-n APD with low dark current, low operating voltage, and high gain is promising for low-power and high-sensitivity Ge PD applications.
