Silicon Wafer CMP Slurry Using a Hydrolysis Reaction Accelerator with an Amine Functional Group Remarkably Enhances Polishing Rate.

Recently, as an alternative solution for overcoming the scaling-down limitations of logic devices with design length of less than 3 nm and enhancing DRAM operation performance, 3D heterogeneous packaging technology has been intensively researched, essentially requiring Si wafer polishing at a very high Si polishing rate (500 nm/min) by accelerating the degree of the hydrolysis reaction (i.e., Si-O-H) on the polished Si wafer surface during CMP. Unlike conventional hydrolysis reaction accelerators (i.e., sodium hydroxide and potassium hydroxide), a novel hydrolysis reaction accelerator with amine functional groups (i.e., 552.8 nm/min for ethylenediamine) surprisingly presented an Si wafer polishing rate >3 times higher than that of conventional hydrolysis reaction accelerators (177.1 nm/min for sodium hydroxide). This remarkable enhancement of the Si wafer polishing rate for ethylenediamine was principally the result of (i) the increased hydrolysis reaction, (ii) the enhanced degree of adsorption of the CMP slurry on the polished Si wafer surface during CMP, and (iii) the decreased electrostatic repulsive force between colloidal silica abrasives and the Si wafer surface. A higher ethylenediamine concentration in the Si wafer CMP slurry led to a higher extent of hydrolysis reaction and degree of adsorption for the slurry and a lower electrostatic repulsive force; thus, a higher ethylenediamine concentration resulted in a higher Si wafer polishing rate. With the aim of achieving further improvements to the Si wafer polishing rates using Si wafer CMP slurry including ethylenediamine, the Si wafer polishing rate increased remarkably and root-squarely with the increasing ethylenediamine concentration.

Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode.

Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 10(5) s with a memory margin of 9.2 × 10(5), program/erase endurance cycles of >10(2) with a memory margin of 8.4 × 10(5), and bending-fatigue-free cycles of ∼1 × 10(3) with a memory margin (I(on)/I(off)) of 3.3 × 10(5).

Effect of core quantum-dot size on power-conversion-efficiency for silicon solar-cells implementing energy-down-shift using CdSe/ZnS core/shell quantum dots.

Silicon solar cells mainly absorb visible light, although the sun emits ultraviolet (UV), visible, and infrared light. Because the surface reflectance of a textured surface with SiNX film on a silicon solar cell in the UV wavelength region (250-450 nm) is higher than ∼27%, silicon solar-cells cannot effectively convert UV light into photo-voltaic power. We implemented the concept of energy-down-shift using CdSe/ZnS core/shell quantum-dots (QDs) on p-type silicon solar-cells to absorb more UV light. CdSe/ZnS core/shell QDs demonstrated clear evidence of energy-down-shift, which absorbed UV light and emitted green-light photoluminescence signals at a wavelength of 542 nm. The implementation of 0.2 wt% (8.8 nm QDs layer) green-light emitting CdSe/ZnS core/shell QDs reduced the surface reflectance of the textured surface with SiNX film on a silicon solar-cell from 27% to 15% and enhanced the external quantum efficiency (EQE) of silicon solar-cells to around 30% in the UV wavelength region, thereby enhancing the power conversion efficiency (PCE) for p-type silicon solar-cells by 5.5%.

The fabrication and characterization of organic light-emitting diodes using transparent single-crystal Si membranes.

For applications such as solar cells and displays, transparent single-crystal Si membranes were fabricated on a silicon-on-insulator (SOI) wafer. The SOI wafer included a buried layer of SiO2 and Si3N4 as an etch-stop layer. The etch-stop layer enabled fabrication of transparent single-crystal Si membranes with various thicknesses, and the thinning technology is described. For membranes with thicknesses of 18, 72 and 5000 nm, the respective optical transparent were 96.9%, 93.7% and 9% for R (red, lambda = 660 nm), 96.9%, 91.4% and 1% for G (green, lambda = 525 nm), and 97.0%, 93.2% and 0% for B (blue, lambda = 470 nm). Organic light-emitting diodes (OLEDs) were then fabricated on transparent single-crystal Si membranes with various top Si thicknesses. OLEDs fabricated on 18, 72 and 5000 nm thick membranes and operated at 6 V demonstrated a luminance of 1350, 443 and 27 cd m(-2) at the current densities of 148, 131 and 1.5 mA cm(-2), respectively.

Multilevel nonvolatile small-molecule memory cell embedded with Ni nanocrystals surrounded by a NiO tunneling barrier.

Four-level nonvolatile small-molecule 4F(2) memory cells were developed with a sandwiched device structure consisting of an upper Al electrode, upper small-molecule layer (Alq(3), aluminum tris(8-hydroxyquinoline)), Ni nanocrystals surrounded by NiO tunneling barrier, lower small-molecule layer, and bottom Al electrode. In particular, an in situ O(2)-plasma oxidation process following Ni evaporation was developed to produce uniformly stable 10 nm Ni nanocrystals surrounded by a NiO tunneling barrier embedded in the small-molecule layer. They presented a memory margin (I(on)/I(off) ratio) of approximately 1 x 10(3), a retention time of more than 10(5) s, an endurance of more than 5 x 10(2) erase-and-program cycles, and multilevel cell (MLC) operation, being a terabit nonvolatile memory-cell. A vertically double-stacked 4F(2) multilevel nonvolatile memory cell was also developed, showing a memory margin of approximately 1 x 10(3) in both the top and bottom memory cells and eight-level cell operation.