After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.
A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of â¼291 µA/µm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.
In this work, extremely thin silicon-on-insulator field effective transistors (ETSOI FETs) are fabricated with an ultra-thin 3 nm ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer. Furthermore, the subthreshold characteristics of the devices with double gate modulation are investigated extensively. Contributing to the advantages of the back-gate voltage coupling effects, the minimum subthreshold swing (SS) value of a 40 nm ETSOI device could be adjusted from the initial 80.8-50 mV/dec, which shows ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is demonstrated. This work shows the feasibility of FE ETSOI FET for ultra-low-power applications with dynamic threshold adjustment.
The ferroelectric field-effect transistors (FeFETs) with HfO2-based ferroelectric layers in the gate stacks are emerging as one of the most promising candidates for the next-generation nonvolatile memory devices due to their scalability and compatibility with conventional Si technology. Moreover, owing to the high radiation hardness of the HfO2-based ferroelectric thin films, HfO2-based FeFETs have attracted great interest in the fields of radiation-hard (rad-hard) memory. However, the reliability of their memory states under irradiation, which represents the validity of the stored information, has not been investigated. Here, we focus on the impact of the total ionizing dose (TID) on erased and programmed states of HfO2-based FeFETs. The TID radiation (X-ray) characteristics of erased and programmed HfO2-based FeFETs are characterized using an on-site read operation. Both the erased and programmed states show robust stability under irradiation at a dose rate of 90 rad(Si)/s, and even at 230 rad(Si)/s, only the erased state shows a slight variation. The possible factors contributing to memory state degradation are discussed. Through the analysis of the threshold voltage shift and subthreshold swing evolution, as well as studies of ferroelectric polarization stability under radiation, it is revealed that the erased state degradation is caused by oxide-trapped charges rather than interface degradation or polarization switching. The physical mechanism of the difference in radiation-induced oxide-trapped charges buildup in programmed and erased FeFETs is analyzed to explain different TID radiation characteristics between them. Our work suggests that the HfO2-based FeFETs have great potential in radiation environment applications.
Nonvolatile logic devices are crucial for the development of logic-in-memory (LiM) technology to build the next-generation non-von Neumann computing architecture. Ferroelectric field-effect transistors (Fe FET) are one of the most promising candidates for LiMs because of high compatibility with mainstream silicon-based complementary metal-oxide semiconductor processes, nonvolatile memory, and low power consumption. However, because of the unipolar characteristics of a Fe FET, a nonlinear XOR or XNOR logic gate function is difficult to realize with a single device. In addition, because single Fe polarization switch modulation is available in the devices, a reconfigurable logic gate usually needs multiple devices to construct and realize fewer logic functions. Here, we introduced polarization-switching (PS) and charge-trapping (CT) effects in a single Fe FET and fabricated a multi-field-effect transistor with bipolar-like characteristics based on advanced 10 nm node fin field-effect transistors (PS-CT FinFET) with 9 nm thick Hf0.5Zr0.5O2 films. The special hybrid effects of charge-trapping and polarization-switching enabled eight Boolean logic functions with a single PS-CT FinFET and 16 Boolean logic functions with two complementary PS-CT FinFETs were obtained with three operations. Furthermore, reconfigurable full 1 bit adder and subtractor functions were demonstrated by connecting only two n-type and two p-type PS-CT FinFET devices, indicating that the technology was promising for LiM applications.
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm-3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device's structure.
Heavily doped polysilicon layers have been widely used in the fabrication of microelectromechanical systems (MEMS). However, the investigation of high selectivity, anisotropy, and excellent uniformity of heavily doped polysilicon etching is limited. In this work, reactive ion etching of undoped and heavily doped polysilicon-based hydrogen bromide (HBr) plasmas have been compared. The mechanism of etching of heavily doped polysilicon is studied in detail. The final results demonstrate that the anisotropy profile of heavily doped polysilicon can be obtained based on a HBr plasma process. An excellent uniformity of resistance of the thermocouples reached ± 2.11%. This technology provides an effective away for thermopile and other MEMS devices fabrication.
The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.
Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
