Mechanism for Local-Atomic Structure Changes in Chalcogenide-based Threshold-Switching Devices.

Threshold-switching devices based on amorphous chalcogenides are considered for use as selector devices in 3D crossbar memories. However, the fundamental understanding of amorphous chalcogenide is hindered owing to the complexity of the local structures and difficulties in the trap analysis of multinary compounds. Furthermore, after threshold switching, the local structures gradually evolve to more stable energy states owing to the unstable homopolar bonds. Herein, based on trap analysis, DFT simulations, and operando XPS analysis, it is determined that the threshold switching mechanism is deeply related to the charged state of Se-Se homopolar defects. A threshold switching device is demonstrated with an excellent performance through the modification of the local structure via the addition of alloying elements and investigating the time-dependent trap evolution. The results concerning the trap dynamics of local atomic structures in threshold switching phenomena may be used to improve the design of amorphous chalcogenides.

All-solid-state spatial light modulator with independent phase and amplitude control for three-dimensional LiDAR applications.

Spatial light modulators are essential optical elements in applications that require the ability to regulate the amplitude, phase and polarization of light, such as digital holography, optical communications and biomedical imaging. With the push towards miniaturization of optical components, static metasurfaces are used as competent alternatives. These evolved to active metasurfaces in which light-wavefront manipulation can be done in a time-dependent fashion. The active metasurfaces reported so far, however, still show incomplete phase modulation (below 360°). Here we present an all-solid-state, electrically tunable and reflective metasurface array that can generate a specific phase or a continuous sweep between 0 and 360° at an estimated rate of 5.4 MHz while independently adjusting the amplitude. The metasurface features 550 individually addressable nanoresonators in a 250 × 250 µm2 area with no micromechanical elements or liquid crystals. A key feature of our design is the presence of two independent control parameters (top and bottom gate voltages) in each nanoresonator, which are used to adjust the real and imaginary parts of the reflection coefficient independently. To demonstrate this array's use in light detection and ranging, we performed a three-dimensional depth scan of an emulated street scene that consisted of a model car and a human figure up to a distance of 4.7 m.

CMOS-compatible Si metasurface at visible wavelengths prepared by low-temperature green laser annealing.

A low-temperature laser crystallization is newly devised for producing polycrystalline silicon (poly-Si) thin films of low-loss, low surface roughness enough for nanoscale patterning, applicable to practical Si metasurface elements on complementary metal-oxide semiconductor (CMOS) electronic architectures in visible lights. The method is based on dielectric encapsulation of an amorphous Si film and subsequent laser-induced local crystallization. Such poly-Si thin film yields order-of-magnitude smaller surface roughness and grain size than those obtained with the conventional laser annealing processes. The mechanism of the formation of small and uniform crystalline grains during solidification is studied to ensure the smooth surfaces enough for nanoscale patterning. By obtaining root mean square of surface roughness <2.49 nm and extinction coefficient <4.8 × 10-2 at 550 nm, visible metasurface color-filter elements are experimentally demonstrated with the resonant transmission-peak efficiency approaching ∼85%. This low-loss poly-Si metasurface is favorably compatible with embedded CMOS electronic architectures in contrast to the conventional thermal annealing processes that often cause failure of electrical device functionalities due to delamination and material-property degradation problems. The proposed fabrication in this study provides a practical method for further development of various Si metasurfaces in the visible domain and their integration with CMOS electronic devices as well.

Time-asymmetric loop around an exceptional point over the full optical communications band.

Topological operations around exceptional points1-8-time-varying system configurations associated with non-Hermitian singularities-have been proposed as a robust approach to achieving far-reaching open-system dynamics, as demonstrated in highly dissipative microwave transmission3 and cryogenic optomechanical oscillator4 experiments. In stark contrast to conventional systems based on closed-system Hermitian dynamics, environmental interferences at exceptional points are dynamically engaged with their internal coupling properties to create rotational stimuli in fictitious-parameter domains, resulting in chiral systems that exhibit various anomalous physical phenomena9-16. To achieve new wave properties and concomitant device architectures to control them, realizations of such systems in application-abundant technological areas, including communications and signal processing systems, are the next step. However, it is currently unclear whether non-Hermitian interaction schemes can be configured in robust technological platforms for further device engineering. Here we experimentally demonstrate a robust silicon photonic structure with photonic modes that transmit through time-asymmetric loops around an exceptional point in the optical domain. The proposed structure consists of two coupled silicon-channel waveguides and a slab-waveguide leakage-radiation sink that precisely control the required non-Hermitian Hamiltonian experienced by the photonic modes. The fabricated devices generate time-asymmetric light transmission over an extremely broad spectral band covering the entire optical telecommunications window (wavelengths between 1.26 and 1.675 micrometres). Thus, we take a step towards broadband on-chip optical devices based on non-Hermitian topological dynamics by using a semiconductor platform with controllable optoelectronic properties, and towards several potential practical applications, such as on-chip optical isolators and non-reciprocal mode converters. Our results further suggest the technological relevance of non-Hermitian wave dynamics in various other branches of physics, such as acoustics, condensed-matter physics and quantum mechanics.

Self-Aligned Multichannel Graphene Nanoribbon Transistor Arrays Fabricated at Wafer Scale.

We present a novel method for fabricating large-area field-effect transistors (FETs) based on densely packed multichannel graphene nanoribbon (GNR) arrays using advanced direct self-assembly (DSA) nanolithography. The design of our strategy focused on the efficient integration of the FET channel and using fab-compatible processes such as thermal annealing and chemical vapor deposition. We achieved linearly stacked DSA nanopattern arrays with sub-10 nm half-pitch critical dimensions (CD) by controlling the thickness of topographic Au confinement patterns. Excellent roughness values (∼10% of CD) were obtained, demonstrating the feasibility of integrating sub-10 nm GNRs into commercial semiconductor processes. Based on this facile process, FETs with such densely packed multichannel GNR arrays were successfully fabricated on 6 in. silicon wafers. With these high-quality GNR arrays, we achieved FETs showing the highest performance reported to date (an on-to-off ratio larger than 10(2)) for similar devices produced using conventional photolithography and block-copolymer lithography.

Sub 50 nm nano-patterns with carbon based spin-on organic hardmask.

Carbon based spin-on organic hardmask (C-SOH) was used as an imprint resin to fabricate sub 50 nm sized patterns. Imprinting of C-SOH was done with a polyurethaneacrylate (PUA) stamp. Patternability and etch resistance of the C-SOH resin was compared to poly(methyl methacrylate) (PMMA). C-SOH can be patterned at the nanosize using imprint lithography and exhibits superior etch resistance, especially for F-based plasmas. Due to the poor etch resistance of imprint resin such as PMMA, it is seldom used as an etch mask to form nano-structures by etching the Si3N4 layer. However, such a nano-structure was able to be formed by etching the Si3N4 layer using C-SOH as an etch mask.

Fabrication of a polyurethane acrylate/polyimide-based polymer mold for a hot embossing process.

A high-thermal-resistance polymer-based flexible imprint mold was developed to be used in a hot embossing process. This mold was readily replicated in a UV curing imprint process and can be used as a mold for hot embossing and thermally curing imprint processes. The nano-sized pattern of this mold was not degraded by soaking at 350 degrees C for 10 min and the pattern fidelity was maintained after 10 separate cyclic heating tests between 0 degrees C and 350 degrees C. The substrate of this flexible mold was PI film, and a UV-cured polyurethane acrylate (PUA) layer was used to form the nano-scale patterns. The durability of this polymeric mold was tested by repetitive hot embossing processes. Nano-scale patterns of the mold were readily transferred to a PMMA layer coated onto a Si substrate by hot embossing lithography at 180 degrees C. After 10 cycles of hot embossing processes, no damage or degradation was observed in the flexible polymer mold. Using this polymer mold, patterns as small as 50 nm were successfully transferred to a Si substrate. Due to the flexibility of the polymer mold, nano-scale patterns were successfully transferred to a non-flat acryl substrate by hot embossing lithography.

The fabrication of a patterned ZnO nanorod array for high brightness LEDs.

In this study, a patterned ZnO nanorod array was formed on the ITO layer of GaN-based light-emitting diodes (LEDs), to increase the light extraction efficiency of the LED. The bi-layer imprinted resin pattern was used for selective growth of the ZnO nanorod array on the ITO layer. Compared to conventional LEDs grown on patterned sapphire substrate (PSS), the deposition of the blanket ZnO layer on the ITO layer increased the light extraction efficiency of the LED by about 10%. Further growth of the ZnO nanorod layer on the blanket ZnO layer increased the light extraction efficiency of the LED by about 23%. In the case that a patterned ZnO nanorod layer was formed on a blanket ZnO layer, the light extraction efficiency increased by about 34%. These enhancements of the device were caused by modulation of the refractive-index in ZnO layers and the surface roughening effects because of the unique design of the pattern, which was nanostructure-in-nanopattern, resulting in the formation of many escape cones on the LED surface.

Thermal imprinting of nano-patterns using thiol-based self-assembled monolayer-treated nickel template.

A highly durable imprint template is essential for the industrialization of nanoimprint lithography (NIL). Conventionally, Si-based materials were used for the fabrication of imprint templates. However, their fabrication is very expensive and they can be easily damaged during repeated imprint processes due to their brittleness and poor mechanical properties. The Ni template has excellent mechanical strength and can be easily and cheaply duplicated by the electroforming process. It has the potential for application to the NIL process if its poor antistiction property, which causes serious detaching issues, is improved. In this study, thin Au and Ti layers were deposited on a Ni template and a thiol-based, hydrophobic, self-assembled monolayer (SAM) layer was stably formed on the Au coated Ni template. Thus, the antistiction property of the Ni template was drastically elevated. Using the prepolymer-based, thermal imprint process and the thiol-based, SAM-coated Ni template, sub-micron sized patterns were successfully formed on the Si substrate.

Fabrication of 70 nm-sized zero residual polymer patterns by thermal nanoimprint lithography.

The formation of a residual layer under the imprinted patterns is commonly observed after the imprinting process. In order to utilize the imprinted patterns into the top-down process, the removal process of the residual layer using oxygen plasma is inevitable. However, the critical dimension of the imprinted patterns can be degraded during the residual layer removal process and this degradation becomes severer for smaller sized patterns. Zero residual layer imprinting therefore has advantages in nano-sized patterning. In this study, 70 nm-narrow polymer patterns with a height of 300 nm were successfully fabricated on a Si wafer without any residual layer using a high aspect ratio template and thin polymer resin layer, after which 70 nm-narrow Cr metal nanowires were formed on the Si wafer through the lift-off process.