Miniaturized preamplifier integration in ultrasound transducer design for enhanced photoacoustic imaging.

Photoacoustic imaging (PAI) utilizes the photoacoustic effect to record both vascular and functional characteristics of a biological tissue. Photoacoustic signals have typically low amplitude that cannot be read efficiently by data acquisition systems. This necessitates the use of one or more amplifiers. These amplifiers are somewhat bulky (e.g., the ZFL-500LN+, Mini-Circuits, USA, or 351A-3-50-NI, Analog Modules Inc., USA). Here, we describe the fabrication and development process of a transducer with a built-in low-noise preamplifier that is encased within the transducer housing. This new, to the best of our knowledge, design could be advantageous for applications where a compact transducer + preamplifier is required. We demonstrate the performance of this compact detection unit in a laser scanning photoacoustic microscopy system by imaging a rat ear ex vivo and a rat brain vasculature in vivo.

Catalyzing satellite communication: A 20W Ku-Band RF front-end power amplifier design and deployment.

This paper presents a groundbreaking Ku-band 20W RF front-end power amplifier (PA), designed to address numerous challenges encountered by satellite communication systems, including those pertaining to stability, linearity, cost, and size. The manuscript commences with an exhaustive discussion of system design and operational principles, emphasizing the intricacies of low-noise amplification, and incorporating key considerations such as noise factors, stability analysis, gain, and gain flatness. Subsequently, an in-depth study is conducted on various components of the RF chain, including the pre-amplification module, driver-amplification module, and final-stage amplification module. The holistic design extends to the inclusion of the display and control unit, featuring the power-control module, monitoring module, and overall layout design of the PA. It is meticulously tailored to meet the specific demands of satellite communication. Following this, a thorough exploration of electromagnetic simulation and measurement results ensues, providing validation for the precision and reliability of the proposed design. Finally, the feasibility of that design is substantiated through systematic system design, prototype production, and exhaustive experimental testing. It is noteworthy that, in the space-simulation environmental test, emphasis is placed on the excellent performance of the Star Ku-band PA within the 13.75GHz to 14.5GHz frequency range. Detailed power scan measurements reveal a P1dB of 43dBm, maintaining output power flatness < ± 0.5dBm across the entire frequency and temperature spectrum. Third-order intermodulation scan measurements indicate a third-order intermodulation of ≤ -23dBc. Detailed results of power monitoring demonstrate a range from +18dBm to +54dBm. Scans of spurious suppression and harmonic suppression, meanwhile, show that the PA evinces spurious suppression ≤ -65dBc and harmonic suppression ≤ -60dBc. Rigorous phase-scan measurements exhibit a phase-shift adjustment range of 0° to 360°, with a step of 5.625°, and a phase-shift accuracy of 0.5dB. Detailed data from gain-scan measurements show a gain-adjustment range of 0dB to 30dB, with a gain flatness of ± 0.5dB. Attenuation error is ≤ 1%. These test parameters perfectly align with the practical application requirements of the technical specifications. When compared to existing Ku-band PAs, our design reflects a deeper consideration of specific requirements in satellite communication, ensuring its outstanding performance and uniqueness. This PA features good stability, high linearity, low cost, and compact modularity, ensuring continuous and stable power output. These features position the proposed system as a leader within the market. Successful orbital deployment not only validates its operational stability; it also makes a significant contribution to the advancement of China's satellite PA technology, generating positive socio-economic benefits.

Investigating the Utility of a Compact Loudspeaker Array for Audiometric Testing.

PURPOSE: This project addressed the uses of a loudspeaker array for audiometric measurements. It sought to evaluate a prototype compact array in terms of the reliability of test results across sound booths. METHOD: A seven-loudspeaker array was developed to deliver sounds from -60° to +60° on an arc with a radius of 0.5 m. The system was equipped with a head position sensing system to maintain the listener's head near the optimal test position. Three array systems were distributed to each of the two test sites for within-subject assessments of booth equivalence on tests of sound localization, speech reception in noise, and threshold detection. A total of 36 subjects participated, 18 at each test site. RESULTS: Results showed excellent interbooth consistency on tests of sound localization using speech and noise signals, including conditions in which one or both ears were covered with a muff. Booth consistency was also excellent on sound field threshold measurements for detecting quasi-diffuse noise bands. Nonequivalence was observed in some cases of speech-in-noise tests, particularly with a small one-person booth. Acoustic analyses of in situ loudspeaker responses indicated that some of the nonequivalent comparisons on speech-in-noise tests could be traced to the effects of reflections. CONCLUSIONS: Overall, the results demonstrate the utility and reliability of a compact array for the assessment of localization ability, speech reception in noise, and sound field thresholds. However, the results indicate that researchers and clinicians should be aware of the reflection effects that can influence the results of sound field tests in which signal and noise levels from separate loudspeakers are critical.

Exonuclease III-propelled DNAzyme walker: an electrochemical strategy for microRNA diagnostics.

MicroRNA detection is crucial for early infectious disease diagnosis and rapid cancer screening. However, conventional techniques like reverse transcription-quantitative polymerase chain reaction, requiring specialized training and intricate procedures, are less suitable for point-of-care analyses. To address this, we've developed a straightforward amplifier based on an exonuclease III (exo III)-propelled DNAzyme walker for sensitive and selective microRNA detection. This amplifier employs a specially designed hairpin probe with two exposed segments for strand recognition. Once the target microRNA is identified by the hairpin's extended single-strand DNA, exo III initiates its digestion, allowing microRNA regeneration and subsequent hairpin probe digestion cycles. This cyclical process produces a significant amount of DNAzyme, leading to a marked reduction in electrochemical signals. The biosensor exhibits a detection range from 10 fM to 100 pM and achieves a detection limit of 5 fM (3σ criterion). Importantly, by integrating an "And logic gate," our system gains the capacity for simultaneous diagnosis of multiple microRNAs, enhancing its applicability in RNA-based disease diagnostics.

Intra-scan RF power amplifier drift correction.

PURPOSE: The drift in radiofrequency (RF) power amplifiers (RFPAs) is assessed and several contributing factors are investigated. Two approaches for prospective correction of drift are proposed and their effectiveness is evaluated. METHODS: RFPA drift assessment encompasses both intra-pulse and inter-pulse drift analyses. Scan protocols with varying flip angle (FA), RF length, and pulse repetition time (TR) are used to gauge the influence of these parameters on drift. Directional couplers (DICOs) monitor the forward waveforms of the RFPA outputs. DICOs data is stored for evaluation, allowing calculation of correction factors to adjust RFPAs' transmit voltage. Two correction methods, predictive and run-time, are employed: predictive correction necessitates a calibration scan, while run-time correction calculates factors during the ongoing scan. RESULTS: RFPA drift is indeed influenced by the RF duty-cycle, and in the cases examined with a maximum duty-cycle of 66%, the potential drift is approximately 41% or 15%, depending on the specific RFPA revision. Notably, in low transmit voltage scenarios, FA has minimal impact on RFPA drift. The application of predictive and run-time drift correction techniques effectively reduces the average drift from 10.0% to less than 1%, resulting in enhanced MR signal stability. CONCLUSION: Utilizing DICO recordings and implementing a feedback mechanism enable the prospective correction of RFPA drift. Having a calibration scan, predictive correction can be utilized with fewer complexity; for enhanced performance, a run-time approach can be employed.

A Low-Noise Low-Power 0.001Hz-1kHz Neural Recording System-on-Chip With Sample-Level Duty-Cycling.

Advances in brain-machine interfaces and wearable biomedical sensors for healthcare and human-computer interactions call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Existing integrated wearable solutions for minimally invasive biopotential recordings are limited in detection range and accuracy due to trade-offs in bandwidth, noise, input impedance, and power consumption. This article presents a 16-channel wide-band ultra-low-noise neural recording system-on-chip (SoC) fabricated in 65nm CMOS for chronic use in mobile healthcare settings that spans a bandwidth of 0.001 Hz to 1 kHz through a featured sample-level duty-cycling (SLDC) mode. Each recording channel is implemented by a delta-sigma analog-to-digital converter (ADC) achieving 1.0 µ V rms input-referred noise over 1Hz-1kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode. In SLDC mode, the power supply is duty-cycled while maintaining consistently low input-referred noise levels at ultra-low frequencies (1.1 µV rms over 0.001Hz-1Hz) and 435 M Ω input impedance. The functionalities of the proposed SoC are validated with two human electrophysiology applications: recording low-amplitude electroencephalogram (EEG) through electrodes fixated on the forehead to monitor brain waves, and ultra-slow-wave electrogastrogram (EGG) through electrodes fixated on the abdomen to monitor digestion.

Power-to-Noise Optimization in the Design of Neural Recording Amplifier Based on Current Scaling, Source Degeneration Resistor, and Current Reuse.

This article presents the design of a low-power, low-noise neural signal amplifier for neural recording. The structure reduces the current consumption of the amplifier through current scaling technology and lowers the input-referred noise of the amplifier by combining a source degeneration resistor and current reuse technologies. The amplifier was fabricated using a 0.18 µm CMOS MS RF G process. The results show the front-end amplifier exhibits a measured mid-band gain of 40 dB/46 dB and a bandwidth ranging from 0.54 Hz to 6.1 kHz; the amplifier's input-referred noise was measured to be 3.1 µVrms, consuming a current of 3.8 µA at a supply voltage of 1.8 V, with a Noise Efficiency Factor (NEF) of 2.97. The single amplifier's active silicon area is 0.082 mm2.

Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications.

A CMOS analog front-end (AFE) local-field potential (LFP) chopper amplifier with stimulation artifact tolerance, improved right-leg driven (RLD) circuit, and improved auxiliary path is proposed. In the proposed CMOS AFE LFP chopper amplifier, common-mode artifact voltage (CMAV) and differential-mode artifact voltage (DMAV) removal using the analog template removal method are proposed to achieve good signal linearity during stimulation. An improved auxiliary path is employed to boost the input impedance and allow the negative stimulation artifact voltage passing through. The common-mode noise is suppressed by the improved RLD circuit. The chip is implemented in 0.18- µm CMOS technology and the total chip area is 5.46-mm2. With the improved auxiliary path, the measured input impedance is larger than 133 M[Formula: see text] in the signal bandwidth and reaches 8.2 G[Formula: see text] at DC. With the improved RLD circuit, the measured CMRR is 131 - 144 dB in the signal bandwidth. Under 60-µs pulse width and 130-Hz constant current stimulation (CCS) with ±1-V CMAV and ±50-mV DMAV, the measured THD at the SC Amp output of fabricated AFE LFP chopper amplifier is 1.28%. The measurement results of In vitro agar tests have shown that with ±1.6-mA CCS pulses injecting to agar, the measured THD is 1.69%. Experimental results of both electrical and agar tests have verified that the proposed AFE LFP chopper amplifier has good stimulation artifact tolerance. The proposed CMOS AFE LFP chopper amplifier with analog template removal method is suitable for real-time closed-loop deep drain stimulation (DBS) SoC applications.

Performance enhancement and PAPR reduction for MIMO based QAM-FBMC systems.

Filter Bank Multi-Carrier (FBMC) is attracting significant interest as a multi-carrier modulation (MCM) approach for future communication systems. It offers numerous advantages in contrast to Orthogonal Frequency Division Multiplexing (OFDM). Nonetheless, similar to many other MCM techniques, FBMC encounters a significant challenge with a high Peak-to-Average Power Ratio (PAPR). Additionally, incorporating Multiple-Input and Multiple-Output (MIMO) into FBMC presents heightened difficulties due to the presence of complex interference and increased computational complexity. In this paper, we first study the performance analysis of MIMO based Quadrature Amplitude Modulation (QAM)-FBMC systems considering the system complexity and interference. To enhance coverage effectively using beamforming with multiple antennas, it is essential to reduce PAPR to minimize the input backoff (IBO) required by nonlinear power amplifiers. Therefore, we propose new PAPR reduction method for MIMO based QAM-FBMC systems leveraging the null space within the MIMO channel using clipping and filtering (CF) technique. The PAPR reduction signals generated in this process are then mapped to the null space of the overall MIMO channel for each frequency block. Through computer simulations using a nonlinear power amplifier model, we illustrate that the proposed method substantially enhances both PAPR and throughput of MIMO based FBMC systems compared to conventional methods.

A 0.67 µV-IIRN super-T Ω-Z IN 17.5 µW/Ch Active Electrode With In-Channel Boosted CMRR for Distributed EEG Monitoring.

We present the design, development, and experimental characterization of an active electrode (AE) IC for wearable ambulatory EEG recording. The proposed architecture features in-AE double common-mode (CM) rejection, making the recording's CMRR independent of typically-significant AE-to-AE gain variations. Thanks to being DC coupled and needless of chopper stabilization for flicker noise suppression, the architecture yields a super-T Ω input impedance. Such a large input impedance makes the AE's CMRR practically immune to electrode-skin interface impedance variations across different recording channels, a critical feature for dry-electrode ambulatory systems. Signal quantization and serialization are also performed in-AE, which enables a distributed system in which all AEs use a single data bus for data/command communication to the backend module, thus significantly improving the system's scalability. Additionally, the presented AE hosts auxiliary modules for (i) detection of an unstable electrode-skin connection through continuous interface impedance monitoring, (ii) dynamic measurement and adjustment of input DC level, and (iii) a CM feedback loop for further CMRR enhancement. The article also presents the development of printed (extrusion) tattoo electrodes and their experimental characterization results with the proposed AE architecture. Besides bio-compatibility, low-cost, pattern flexibility, and quick fabrication process, the printed electrodes offer a very stable electrode-skin connection, conform to scalp shape, and exhibit consistent performance under various bending curvatures. Analog circuit blocks of the presented AE architecture are designed and fabricated using a standard 180 nm CMOS technology, and the [Formula: see text] IC is integrated with off-chip low-power digital modules on a PCB to form the AE. Our measurement results show a CMRR of 82.2 dB (at 60 Hz), amplification voltage gain of 52.8 dB, a bandwidth of 0.2-400 Hz, ±500 mV input DC offset tolerance, An input impedance [Formula: see text], and 0.67 µV RMS integrated input referred noise (0.5-100 Hz), while consuming 17.5 µW per channel. All auxiliary modules are tested experimentally, and the entire system is validated in-vivo, for both ECG and EEG recording.

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-µm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 µW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

A LFP/AP Mode Reconfigurable Analog Front-End Combining an Electrical EEEG-iEEG Model for the Closed-Loop VNS.

This article presents a local field potential (LFP)/action potential (AP) mode reconfigurable analog front-end (AFE) dedicated for the closed-loop vagus nerve stimulator (VNS). It combines an inverse electrical model of the intracranial electroencephalogram (iEEG) conducting in the brain tissues and been recorded at scalp as the extended electroencephalogram (EEEG). The AFE contains a LFP/AP mode reconfigurable EEEG preamplifier, a tunable integrator to compensate the effect of either the recording electrodes or head tissues, and an adder. The LFP/AP mode reconfigurable EEEG preamplifier consists of a tunable chopper-stabilized amplifier (CSA) and a 2nd-order tunable low pass filter (LPF). For better separation of LFP and AP signals, a high-order DC servo loop (DSL) characterized as a 2nd-order DSL in parallel with a 1st-order DSL is exploited in the tunable CSA to achieve a tunable high-pass frequency with a stopband attenuation slope (SAS) of +40 dB/dec. In addition, the tunable LPF can obtain a tunable low-pass frequency with a SAS of -40 dB/dec and provide additional 20 dB gain for AP signals. Fabricated in a SMIC 180 nm CMOS technology, and in the LFP band (0.5 Hz-200 Hz) and AP band (300 Hz-5 kHz), the measured mid-band gains of the LFP/AP mode reconfigurable EEEG preamplifier are 39.6 dB and 59.5 dB, the input-referred noises (IRNs) are 2.2 µVrms and 6.3 µVrms, the DC/in-band input impedances are 1.27/1.26 GΩ and 0.3/0.22 GΩ, respectively. The power consumption per channel AFE is 6.3 µW, and the die area is 1.4 mm × 0.25 mm.

A High CMRR Differential Difference Amplifier Employing Combined Input Pairs for Neural Signal Recordings.

This article introduces a Combined .symmetrical and complementary Input Pairs (CIP) of a Differential Difference Amplifier (DDA), to boost the total Common-Mode Rejection Ratio (CMRR) for multi-channel neural signal recording. The proposed CIP-DDA employs three input pairs (transconductors). The dc-coupled input neural signal connection, via the gate terminal of the first transconductor, yields a high input impedance. The high-pass corner frequency and dc quiescent operation point are stabilized by the second transconductor. The calibration path of differential-mode gain and Common-Mode Feedback (CMFB) is provided by the proposed third transconductor. The parallel connection has no need for extra voltage headroom of input and output. The proposed CIP-DDA is targeted at integrated circuit realization and designed in a 0.18-µm CMOS technology. The proposed CIP-DDAs with system CMFB achieve an average CMRR of 103 dB, and each channel consumes circa 3.6 µW power consumption.

A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications.

A second-order voltage-controlled oscillator (VCO)-based continuous-time sigma-delta modulator (CTSDM) for current-sensing readout applications is proposed. Current signals from the sensor can directly be quantized by the proposed VCO-based CTSDM, which does not require any extra trans-impedance amplifiers. With the proportional-integral (PI) structure and a VCO phase integrator, the capability of second-order noise shaping is available to reduce the in-band quantization noise. The PI structure can be simply realized by a resistor in series with the integrating capacitor, which can reduce the architecture complexity and maintain the stability of the system. The current-steering digital-to-analog converter with tail and sink current sources is used on the feedback path for the subtraction of the current-type input signal. All the components of the circuit are scaling friendly and applicable to current-sensing readout applications in the Internet of Things (IoT). The proposed VCO-based CTSDM implemented in a 0.18-µm standard CMOS process has a measured signal-to-noise and distortion ratio (SNDR) of 74.6 dB at 10 kHz bandwidth and consumes 44.8 µw only under a supply voltage of 1.2 V, which can achieve a Figure-of-Merit (FoM) of 160.76 dB.

Development of a low-cost, compact, wireless, 16 - channel biopotential data acquisition, signal conditioning and arbitrary waveform stimulator.

The health and fitness of the human body rely heavily on physiological parameters. These parameters can be measured using various tools such as ECG, EMG, EEG, EOG, among others, to obtain real-time physiological data. Analysing the bio-signals obtained from these measurements can provide valuable information that can be used to improve health-care in terms of observation, diagnosis, and treatment. In bio-signal pattern recognition applications, more channels provide multiple information simultaneously. Different biosignal acquisition devices are available in the market, most of which are designed for specific signals like ECG, EMG, EEG etc The gain of the amplifiers and frequency of the filters are designed as per the targeted signals; due to which one device cannot be used for other signals. Also, most of the systems are wired system which is not comfortable for animal studies. In this paper, a low-cost, compact, wireless, 16 channel biopotential data acquisition system with integrated electrical stimulator is designed and implemented. There are several novel and flexible design approaches were incorporated in the proposed design like (1) It has user selectable digital filter in each channel based on the signal frequencies like ECG, EMG, EEG, EOG. The same system will be used to acquire different signals simultaneously. (2) It has variable gain with a configurable analog bandpass filter. (3) It can acquire signals from 4 patients simultaneously. (4) The system is capable to acquire signal from both two-electrode as well as three-electrode configurations. (5) It has integrated stimulator with trapezoidal, charge-balanced, biphasic stimulus output with near zero DC level and user selectable pulse duration or frequency of the stimulus. The developed system has the ability to acquire and transmit data wirelessly in real-time at a high transfer rate. To validate the performance of the system, tests were conducted on the acquired signals using a simulator.

Wireless and Wearable Auditory EEG Acquisition Hardware Using Around-The-Ear cEEGrid Electrodes.

Aside from a clinical interest in electroencephalography (EEG) measurements of real-time data with a high temporal resolution, there is a demand for acquisition systems that are operable outside the laboratory environment. In this study, we designed a wearable and low-power EEG system for multichannel EEG acquisition beyond the lab doors. Around-the-ear cEEGrid electrodes are used to capture 8 biopotential channels which are amplified by low-power precision instrumentation amplifiers and passed on to an analog-to-digital converter (ADC). An ESP32 micro-controller captures the data from the ADC and stores it on an external SD card. The proposed system is compared to a state-of-the-art EEG acquisition system (BioSemi) to assess its diagnostic power for auditory brainstem responses (ABRs). The recordings with our portable system match, and even outperform, the baseline method's specifications. Our hardware opens up new avenues for fast sampling-rate auditory EEG recordings that can be used in hearing diagnostics, damage prevention and treatment follow up.

A Low-Power High Input Range PPG Readout Amplifier with a Current Buffer Input.

This paper presents ultra-low power photoplethysmography (PPG) readout circuits. The proposed system architecture uses a current buffer between the photodiode (PD) and the transimpedance amplifier (TIA) to isolate the large parasitic capacitance of the PD leading to improves the power consumption of the TIA. A class AB topology is exploited at the output of the amplifier, which allows for increased drive capability without the use of auxiliary circuits. The maximum input current range of the TIA is 160 µA, so the large DC current of the input signal does not saturate the circuit. In the LED driver circuit, by varying the duty cycle of a pulse wave modulation (PWM) signal, the ON and OFF times of the circuits. The amplifier and LED driver are manufactured in the 130 nm TSMC CMOS process. The power consumption of the circuits with a duty cycle of 1% is 3.28 µW (at VDD = 1.2V).Clinical Relevance- Vital signs are becoming a very important research topic due to the recent prevalence of COVID-19 and other respiratory diseases. This research aims to develop and interface circuits to monitor vital signs including blood pressure, heart rate, and respiratory rate to study respiratory disease, drug safety, and efficacy.

Design, implementation, and preliminary in-vivo assessment of a high-CMRR low-NEF wireless EEG miniaturized platform.

This work presents the design, manufacture, test, and preliminary in-vivo assessment of the proof-of-concept of a miniaturized wireless platform for acquiring electroencephalography signals, where the input stage is a high-CMRR current-efficiency custom-made integrated neural preamplifier.Clinical relevance- Small, low-power consumption, wireless, wearable devices for chronically monitoring EEG recordings may contribute to the diagnosis of transient neurological events, the characterization and potential forecasting of epileptic seizures, and provide signals for controlling prosthetic and aid devices.

Multi-channel Wireless Implantable Brain-Computer Interface System.

The implantable brain-computer interface has been widely used in recent years due to its great application potential and research value. Few neural implants have been designed to gather neural spikes, which require a higher sampling frequency than ECoG and LFPs. These systems are still constrained by low channel counts and their bulky size. Furthermore, wire connection is still used in many neural interfaces for further data analysis, facing challenges such as tissue infection, limited movement, and increased noise interference. To address the aforementioned problems, this paper presents a compact multi-channel wireless implantable brain-computer interface system that meets the requirements of spike signals collection and miniaturization. A WiFi module is utilized to transmit information between the system and terminal equipment to eliminate the tethering effects. A 128-channel signal acquisition module, consisting of two pieces of commercial digital electrophysiology amplifier chips, is designed to realize high channel counts for capturing spike events. The proposed system has successfully recorded the analog spike signals from a digital neural signal simulator.

A multi-objective optimization based doherty power amplifier and its matching network optimization method.

In the actual design process of traditional power amplifiers, there is a problem of being cumbersome and unable to simultaneously meet low power and saturation modes. Therefore, an improved multi-objective optimization algorithm proposed by decomposition is introduced to optimize its matching network to achieve overall optimization design of power amplifiers. The algorithm, matching network, and optimized power amplifier performance are simulated and verified. The experimental outcomes denote that on the logic function with Zener diode transistor, the proposed algorithm has a mean generation distance index of 5.03E-3, which is lower than most algorithms. Its overall comprehensive performance is better than the comparison algorithm, and compared to the comparison algorithm, it converges more quickly in the early stage of iteration on 1 and 2, and tends to stabilize in the 40th generation, and completes convergence in the 80th generation. In addition, the optimal solution has already begun to appear around the 25th generation and reached saturation around the 70th generation. At the same time, in the actual working bandwidth, the optimized power amplifier saturation efficiency reaches 51.5%~61.9%, and the efficiency at 6dB power backoff is about 44.4%~56.5%. Overall, the algorithm proposed in the study is effective in optimizing power amplifiers and their matching networks, effectively solving the problem of insufficient efficiency in low power modes in traditional designs.