A Comprehensive Study of NF3-Based Selective Etching Processes: Application to the Fabrication of Vertically Stacked Horizontal Gate-All-around Si Nanosheet Transistors.

In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF3/O2/Ar gas mixture is used to etch back the SiN film. The impact of the O2/NF3 ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O2 into NF3/Ar discharge, the selectivity increases sharply, but when the ratio of O2/NF3 is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O2/NF3 = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET).

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance (Rth) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD-top-VSS (TDTS), bottom-VDD-bottom-VSS (BDBS), and bottom-VDD-top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The Rth of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the Ion is increased by 2% for NFET and 7% for PFET.

Non-Buffer Epi-AlGaN/GaN on SiC for High-Performance Depletion-Mode MIS-HEMTs Fabrication.

A systematic study of epi-AlGaN/GaN on a SiC substrate was conducted through a comprehensive analysis of material properties and device performance. In this novel epitaxial design, an AlGaN/GaN channel layer was grown directly on the AlN nucleation layer, without the conventional doped thick buffer layer. Compared to the conventional epi-structures on the SiC and Si substrates, the non-buffer epi-AlGaN/GaN structure had a better crystalline quality and surface morphology, with reliable control of growth stress. Hall measurements showed that the novel structure exhibited comparable transport properties to the conventional epi-structure on the SiC substrate, regardless of the buffer layer. Furthermore, almost unchanged carrier distribution from room temperature to 150 °C indicated excellent two-dimensional electron gas (2DEG) confinement due to the pulling effect of the conduction band from the nucleation layer as a back-barrier. High-performance depletion-mode MIS-HEMTs were demonstrated with on-resistance of 5.84 Ω·mm and an output current of 1002 mA/mm. The dynamic characteristics showed a much smaller decrease in the saturation current (only ~7%), with a quiescent drain bias of 40 V, which was strong evidence of less electron trapping owing to the high-quality non-buffer AlGaN/GaN epitaxial growth.

A Novel Atomic-Level Post-Etch-Surface-Reinforcement Process for High-Performance p-GaN Gate HEMTs Fabrication.

A novel atomic-level post-etch-surface-reinforcement (PESR) process is developed to recover the p-GaN etching induced damage region for high performance p-GaN gate HEMTs fabrication. This process is composed of a self-limited surface modification step with O2 plasma, following by an oxide removal step with BCl3 plasma. With PESR process, the AlGaN surface morphology after p-GaN etching was comparable to the as-epitaxial level by AFM characterization, and the AlGaN lattice crystallization was also recovered which was measured in a confocal Raman system. The electrical measurement further confirmed the significant improvement of AlGaN surface quality, with one-order of magnitude lower surface leakage in a metal-semiconductor (MS) Schottky-diode and 6 times lower interface density of states (Dit) in a MIS C-V characterization. The XPS analysis of Al2O3/AlGaN showed that the p-GaN etching induced F-byproduct and Ga-oxide was well removed and suppressed by PESR process. Finally, the developed PESR process was successfully integrated in p-GaN gate HEMTs fabrication, and the device performance was significantly enhanced with ~20% lower of on-resistance and ~25% less of current collapse at Vds,Q bias of 40 V, showing great potential of leverage p-GaN gate HEMTs reliability.

In Situ H-Radical Surface Treatment on Aluminum Gallium Nitride for High-Performance Aluminum Gallium Nitride/Gallium Nitride MIS-HEMTs Fabrication.

In this work, we demonstrated a low current collapse normally on Al2O3/AlGaN/GaN MIS-HEMT with in situ H-radical surface treatment on AlGaN. The in situ atomic pretreatment was performed in a specially designed chamber prior to the thermal ALD-Al2O3 deposition, which improved the Al2O3/AlGaN interface with Dit of ~2 × 1012 cm-2 eV-1, and thus effectively reduced the current collapse and the dynamic Ron degradation. The devices showed good electrical performance with low Vth hysteresis and peak trans-conductance of 107 mS/mm. Additionally, when the devices operated under 25 °C pulse-mode stress measurement with VDS,Q = 40 V (period of 1 ms, pulse width of 1 µs), the dynamic Ron increase of ~14.1% was achieved.

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device.

In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress caused serious deformation to suspended nanosheets. With the guidance of the experiment result, based on simulation studies using the COMSOL Multiphysics and Sentaurus tools, it is confirmed that the stress applied on the channel from source/drain plays an important role in nanosheet deformation during the fabrication process. The deformation of Si nanosheets would cause a serious degradation of the device performance due to an inability to control the work function of the metal gate. This study proposed that the uniformly stacked GAA nanosheets structure could be successfully demonstrated with suitable channel stress engineering provided by fitting S/D size and an appropriate channel length. The conclusions provide useful guidelines for future stacked GAA transistors' design and fabrication.

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation.

The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si0.7Ge0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets.

A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology.

High Selectivity, Low Damage ICP Etching of p-GaN over AlGaN for Normally-off p-GaN HEMTs Application.

A systematic study of the selective etching of p-GaN over AlGaN was carried out using a BCl3/SF6 inductively coupled plasma (ICP) process. Compared to similar chemistry, a record high etch selectivity of 41:1 with a p-GaN etch rate of 3.4 nm/min was realized by optimizing the SF6 concentration, chamber pressure, ICP and bias power. The surface morphology after p-GaN etching was characterized by AFM for both selective and nonselective processes, showing the exposed AlGaN surface RMS values of 0.43 nm and 0.99 nm, respectively. MIS-capacitor devices fabricated on the AlGaN surface with ALD-Al2O3 as the gate dielectric after p-GaN etch showed the significant benefit of BCl3/SF6 selective etch process.