Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits.

In this article, for the first time, we explained a detailed physical insight for negative differential resistance (NDR) to positive differential resistance (PDR) transition in a ferroelectric (FE)-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on fully depleted silicon on insulator (FDSOI)-NCFET. The NDR-to-PDR transition occurs due to FE layer capacitance changes from a negative to positive state during channel pinchoff. This, in turn, results in a valley point in the output characteristic ( IDS - VDS ) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical electric field through the FE layer in the channel pinchoff region using body bias ( VBB ). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Furthermore, we have utilized the modulation in the NDR-to-PDR transition due to VBB for designing a current mirror. Results show that the output current ( IOUT ) variation due to VDS reduces from ~8% to ~2% with VBB . We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS - VDS . We have also explored the device scaling effect on the amplifier gain and found that ~ 2.23× gain can be increased with smaller channel length and higher device width.

BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective.

Till date, the existing understanding of negative differential resistance (NDR) is obtained from metal-ferro-metal-insulator-semiconductor (MFMIS) FET, and it has been utilized for both MFMIS and metal-ferro-insulator-semiconductor (MFIS) based NCFETs. However, in MFIS architecture, the ferroelectric capacitance (CFE) is not a lumped capacitance. Therefore, for MFIS negative capacitance (NC) devices, the physical explanation which governs the NDR mechanism needs to be addressed. In this work, for the first time, we present the first principle explanation of the NDR effect in MFIS NC FDSOI. We found that the output current variation with the drain to source voltage (VDS), (i.e.gds) primarily depends upon two parameters: (a)VDSdependent inversion charge gradient (∂n/∂VDS); (b)VDSsensitive electron velocity (∂v/∂VDS), and the combined effect of these two dependencies results in NDR. Further, to mitigate the NDR effect, we proposed the BOX engineered NC FDSOI FET, in which the buried oxide (BOX) layer is subdivided into the ferroelectric (FE) layer and the SiO2layer. In doing so, the inversion charge in the channel is enhanced by the BOX engineered FE layer, which in turn mitigates the NDR and a nearly zerogdswith a minimal positive slope has been obtained. Through well-calibrated TCAD simulations, by utilizing the obtained positivegds, we also designed aVDSindependent constant current mirror which is an essential part of analog circuits. Furthermore, we discussed the impact of the FE parameter (remanent polarization and coercive field) variation on the device performances. We have also compared the acquired results with existing literature on NC-based devices, which justifies that our proposed structure exhibits complete diminution of NDR, thus enabling its use in analog circuit design.