A Study on the Role of Pre-Cleaning and a New Method to Strengthen Gate Oxide Quality.

Isopropyl alcohol (IPA) has been conventionally used for pre-cleaning processes. As the device size decreased, the gate oxide layer became thinner. As a result, the quality of the gate oxide was degraded by a pre-cleaning process, and oxide reliabilities and product yield were affected. In this study, we investigate whether the carbon generated on the silicon interface after the IPA drying process might have induced gate oxide breakdown. Time-dependent dielectric breakdown (TDDB) failure increased in frequency since carbon contaminations were increased in the oxide according to the amount of IPA. Organic contaminations resulted in a lower energy level, and electron tunneling occurred through the gate oxide. When an external electric field was applied, organic materials in the gate oxide layer were aligned, and a percolation path formed to cause breakdown. Finally, we suggest a new cleaning method using carbon-free O3 deionized (DI) water as a dry-cleaning method to improve oxide dielectric breakdown. An O3 DI dry cleaning process could reduce carbon particles in the oxide layer and decrease gate oxide failure by 7%.

Effect of Heat Budget After Capacitor Formation on the Leakage Current Characteristics of ZrO2-Based High-k Dielectrics for Next-Generation Dynamic Random-Access Memory Capacitors.

Successful development of 20 nm or smaller dynamic random-access memory (DRAM) requires reduction of the leakage current in capacitors with high-k dielectrics. To reduce the leakage current of the capacitor, we fabricated a ZrO2-based metal-insulator-metal (MIM) capacitor and investigated changes in leakage current characteristics associated with heat budget following capacitor formation. Leakage current characteristics were drastically degraded by applying an additional heat treatment to the MIM capacitor. Through detailed analysis of leakage versus bias voltage (I-V) characteristics, dielectric constants, and high-resolution transmission electron microscopy (HR-TEM) findings, we determined that the leakage current degradation was caused by an increase in Poole-Frenkel (P-F) emission due to an increase in defect density in the dielectrics and an increase in the dielectric constant due to enhancement of the crystallinity of ZrO2. Based on the experimental results, we propose a new, simple strategy to reduce leakage current without changing the capacitor structure or material used in the DRAM manufacturing process. This simple approach will not only enable mass production of 20 nm DRAM, but also contribute to the development of next-generation DRAMs by reducing the leakage current of the capacitor.

Direct evidence of flat band voltage shift for TiN/LaO or ZrO/SiO2 stack structure via work function depth profiling.

We demonstrated that a flat band voltage (VFB) shift could be controlled in TiN/(LaO or ZrO)/SiO2 stack structures. The VFB shift described in term of metal diffusion into the TiN film and silicate formation in the inserted (LaO or ZrO)/SiO2 interface layer. The metal doping and silicate formation confirmed by using transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) line profiling, respectively. The direct work function measurement technique allowed us to make direct estimate of a variety of flat band voltages (VFB). As a function of composition ratio of La or Zr to Ti in the region of a TiN/(LaO or ZrO)/SiO2/Si stack, direct work function modulation driven by La and Zr doping was confirmed with the work functions obtained from the cutoff value of secondary electron emission by auger electron spectroscopy (AES). We also suggested an analytical method to determine the interface dipole via work function depth profiling.

Defect visualization of Cu(InGa)(SeS)2 thin films using DLTS measurement.

Defect depth profiles of Cu (In1-x,Gax)(Se1-ySy)2 (CIGSS) were measured as functions of pulse width and voltage via deep-level transient spectroscopy (DLTS). Four defects were observed, i.e., electron traps of ~0.2 eV at 140 K (E1 trap) and 0.47 eV at 300 K (E2 trap) and hole traps of ~0.1 eV at 100 K (H1 trap) and ~0.4 eV at 250 K (H2 trap). The open circuit voltage (VOC) deteriorated when the trap densities of E2 were increased. The energy band diagrams of CIGSS were also obtained using Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), and DLTS data. These results showed that the valence band was lowered at higher S content. In addition, it was found that the E2 defect influenced the VOC and could be interpreted as an extended defect. Defect depth profile images provided clear insight into the identification of defect state and density as a function of depth around the space charge region.

Electrical Properties and Reliability Analysis of Solution-Processed Indium Tin Zinc Oxide Thin Film Transistors with O2-Plasma Treatment.

In this paper, we report the effects of O2-plasma treatment on the reliability and electrical properties of indium tin zinc oxide (ITZO) films. Excellent electrical properties, including a saturation mobility (µsat) of ~20.2 cm2/V · s, a threshold voltage (VTH) of ~-6.8 V, a sub-threshold swing (S.S) of ~0.956 V/decade, and an on/off current ratio (ION/OFF) of ~10(5) can be found with a molarity of 0.4 M and ratio of In:Zn:Sn = 2:1:2. Following O2-plasma treatment, it was confirmed that the electrical properties of the ITZO films are improved when compared to the untreated films. The devices showed a decreased S.S of ~0.51 V/decade, while the VTH and ION/OFF tended to increase. To determine the reliability of a-ITZO TFTs, we analyzed the electrical characteristics according to gate bias stress, VG,stress = 10 V for 4000 s. Improved reliability was confirmed when compared with the variation in threshold voltage prior to O2-plasma treatment, most likely stemming from a smooth surface on the active layer as a result of O2-plasma treatment. We were able to obtain a solution a-ITZO film transmittance of 92% in the visible light region (400~700 nm). These results show that a-ITZO TFTs fabricated via solution process with optimized molar ratio exhibit good electrical properties. a-ITZO films fabricated via spin-coating are a visible alternative to those fabricated via high-cost sputtering methods, and are applicable in flexible and transparent electronics.

Electrical Properties of Solution Processed In-Ga-ZnO Thin Film Transistors with Multi-Stacked Active Layer.

In this study, we prepared solution-based In-Ga-ZnO thin film transistors (IGZO TFTs) having a multistacked active layer. The solution was prepared using an In:Zn = 1:1 mole ratio with variation in Ga content, and the TFTs were fabricated by stacking layers from the prepared solutions. After we measured the mobility of each stacked layer, the saturation mobility showed values of 0.8, 0.6 and 0.4 (cm2/Vs), with an overall decrease in electrical properties. The interface formed between the each layers affected the current path, resulting in reduced electrical performance. However, when the gate bias VG = 10 V was applied for 1500 s, the threshold voltage shift decreased in the stack. The uniformity of the active layer was improved in the stacked active layer by filling the hole formed during pre-baking, resulting in improved device stability. Also, the indium ratio was increased to enhance the mobility from 0.86 to 3.47. These results suggest high mobility and high stability devices can be produced with multistacked active layers.

Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress.

In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNx dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNx/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is "turn-around" behavior. In the second stage, the Vth moves from -1.63 V to -2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.

Preparation and Characterization of P-Type and N-Type Doped Expanded Graphite Polymer Composites for Thermoelectric Applications.

In this work, we demonstrate that expanded graphite can be sufficiently dispersed in polymer solution to form suspensions. Thin composite films were prepared by casting and drying the suspensions. The thermoelectric properties of expanded graphite (ExG)-polymer composites were easily modified by chemical doping. Electrically and thermally insulating polymers of PC, PS, and PMMA served as matrix materials. ExG composite films in PC, PMMA, and PS were prepared using thionyl chloride as the p-type dopant and PEI as the n-type dopant. By comparing the electrical conductivity and Seebeck coefficient values of the composite films, we observed that use of an electron acceptor material (thionyl chloride) in composites enhanced electrical conductivity and reduced the value of the positive Seebeck coefficient, which are p-type doping effects. In contrast, when the donor material PEI was used, there was an increase in electrical conductivity and changes in the value and sign of the Seebeck coefficient from positive to negative, confirming n-type doping.

Temperature-dependent electrical characteristics of c-Si and CIGS solar cells.

We characterized the electrical behavior of crystalline silicon (c-Si) and Cu(In(1-x)Ga(x))Se2 (CIGS) solar cells by current-voltage (I-V) and capacitance-voltage (C-V) methods. We investigated the temperature-dependent carrier transport mechanism by determining the parameters of ideality factor (n) and activation energy (E(a)) deduced from I-V measurements. CLGS solar cells, as a function of temperature, showed drastic changes in n and E(a) in the space charge region (SCR) that forms near the ZnS/CIGS interface. Furthermore, by using a C-V measured substrate doping profiling method, we confirmed that the CIGS absorption layer had a graded band-gap structure from the end point of the SCR to the CIGS/Mo back contacts, while c-Si solar cells had a uniformly doped carrier concentration.