Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO2 Electrolyte Gate Insulator.

Artificial synapses with ideal functionalities are essential in hardware neural networks to allow for energy-efficient analog computing. Electrolyte-gated transistors (EGTs) are promising candidates for artificial synaptic devices due to their low voltage operations supported by large specific capacitances of electrolyte gate insulators (EGIs). We investigated the synapse transistor employing an In-Ga-Zn-O channel and a Li-doped ZrO2 (LZO) EGI so as to improve the short-term plasticity (STP) and long-term potentiation (LTP). The LZO EGIs showed distinct differences in characteristics depending on the Li doping concentration, and we adopted the optimum doping concentration of 10%. Based on the strong electric double layer effect secured from the LZO, we successfully demonstrated excellent synaptic operations with gradual modulations of excitatory synaptic plasticity with variations in amplitude, width, and number of applied pulse spikes. The introduction of the LZO EGI was verified to improve typical short-term plasticity such as paired-pulse facilitation. Furthermore, by minutely controlling the pulse spike conditions, the conversion to LTP from STP was clearly accomplished while implementing the anti-Hebbian spike timing-dependent plasticity. Finally, the array configuration of synaptic devices, which is essential for realizing neuromorphic computing, was also demonstrated. In a 3 × 3 array architecture, the weighted-sum operation was well emulated to assign multilevels in seven states with the pulse width modulation scheme.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In-Ga-Zn-O bilayer channel configuration.

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In-Ga-Zn-O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec-1), and high current drivability (13.6µAµm-1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm-1for 104s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subµm Channel Lengths.

Roles of oxygen interstitial defects located in the In-Ga-Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry analysis that the excess oxygens increased with increasing the In contents within the IGZO channels. While the device using the IGZO channel with an In/Ga ratio of 0.2 did not show marked differences with the variations in the oxidant types during the gate-stack formation, the device characteristics were severely deteriorated with increasing the In/Ga ratio to 1.4, when the Al2O3 gate insulator (GI) was prepared with the H2O oxidants (H2O-Al2O3) due to a higher amount of excess oxygen in the channel. Additionally, during the deposition process of the Al-doped ZnO (AZO) gate electrode (GE) replacing from the indium-tin oxide (ITO) GE, the thermal annealing effect at 180 °C facilitated the passivation of oxygen vacancy and the strengthening of metal-oxygen bonding, which could stabilize the TFT operations. From these results, the gate-stack structure employing O3-processed Al2O3 GI (O3-Al2O3) and AZO GE (OA) was suggested to be most suitable for the device using IGZO channel with a higher In content. On the other hand, the device employing H2O-Al2O3 GI and AZO GE exhibited larger negative shifts of threshold voltage (VTH) under positive-bias-temperature stress (PBTS) condition than the device employing O3- Al2O3 GI and ITO GE due to larger hydrogen contents within the gate stacks. Anomalous negative shifts of VTH were accelerated with increasing the In contents of the IGZO channel. When the channel length of the fabricated device were scaled down to submicrometer regime, the OA gate stacks successfully alleviated the short-channel effects.

Implementation of oxide vertical channel TFTs with sub-150 nm channel length using atomic-layer deposited IGZO active and HfO2gate insulator.

We fabricated vertical channel thin film transistors (VTFTs) with a channel length of 130 nm using an ALD In-Ga-Zn-O (IGZO) active channel and high-k HfO2gate insulator layers. Solution-processed SiO2thin film, which exhibited an etch selectivity as high as 4.2 to drain electrode of indium-tin oxide, was introduced as a spacer material. For the formation of near-vertical sidewalls of the spacer patterns, the drain and spacer were successively patterned by means of two-step plasma etching technique using Ar/Cl2and Ar/CF4etch gas species, respectively. The SiO2spacer showed smooth surface morphology (Rq = 0.45 nm) and low leakage current component of 10-6A cm-2at 1 MV cm-1, which were suggested to be appropriate for working as spacer and back-channel. The fabricated VTFT showed sound transfer characteristics and negligible shifts in threshold voltage against the bias stresses of +5 and -5 V for 104s, even though there was abnormal increase in off-currents under the positive-bias stress due to the interactions between hydrogen-related defects and carriers. Despite the technical limitations of patterning process, our fabricated prototype IGZO VTFTs showed good operation stability even with an ultra-short channel length of 130 nm, demonstrating the potential of ALD IGZO thin film as an alternative channel for highly-scaled electronic devices.

Comparative studies on vertical-channel charge-trap memory thin-film transistors using In-Ga-Zn-O active channels deposited by sputtering and atomic layer depositions.

Vertical-channel charge-trap memory thin film-transistors (V-CTM TFTs) using oxide semiconductors were fabricated and characterized, in which In-Ga-Zn-O (IGZO) channels were prepared by sputtering and atomic-layer deposition (ALD) methods to elucidate the effects of deposition process. The vertical-channel gate stack of the fabricated device was verified to be well implemented on the vertical sidewall of the spacer patterns due to excellent step-coverage and self-limiting mechanisms of ALD process. The V-CTM TFTs using ALD-IGZO channel exhibited a wide memory window (MW) of 15.0 V at a VGS sweep of ±20 V and a large memory margin of 1.6 × 102 at a program pulse duration as short as 5 ms. The programmed memory margin higher than 105 did not experience any degradation with time evolution for 104 s. The mechanical durability was also evaluated after the delamination process of polyimide (PI) film. There were no marked variations in charge-trap-assisted MW even at a curvature radius of 1 mm and programmed memory margin even after repeated program operations of 104 cycles. The introduction of ALD process for the formation of IGZO active channel was suggested as a main process parameter to ensure the excellent memory device characteristics of the V-CTM TFTs.