Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits.

In this article, for the first time, we explained a detailed physical insight for negative differential resistance (NDR) to positive differential resistance (PDR) transition in a ferroelectric (FE)-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on fully depleted silicon on insulator (FDSOI)-NCFET. The NDR-to-PDR transition occurs due to FE layer capacitance changes from a negative to positive state during channel pinchoff. This, in turn, results in a valley point in the output characteristic ( IDS - VDS ) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical electric field through the FE layer in the channel pinchoff region using body bias ( VBB ). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Furthermore, we have utilized the modulation in the NDR-to-PDR transition due to VBB for designing a current mirror. Results show that the output current ( IOUT ) variation due to VDS reduces from ~8% to ~2% with VBB . We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS - VDS . We have also explored the device scaling effect on the amplifier gain and found that ~ 2.23× gain can be increased with smaller channel length and higher device width.

Efficient implementation of LMS adaptive filter-based FECG extraction on an FPGA.

In this Letter, the field programmable gate array (FPGA) implementation of a foetal heart rate (FHR) monitoring system is presented. The system comprises a preprocessing unit to remove various types of noise, followed by a foetal electrocardiogram (FECG) extraction unit and an FHR detection unit. To improve the precision and accuracy of the arithmetic operations, a floating-point unit is developed. A least mean squares algorithm-based adaptive filter (LMS-AF) is used for FECG extraction. Two different architectures, namely series and parallel, are proposed for the LMS-AF, with the series architecture targeting lower utilisation of hardware resources, and the parallel architecture enabling less convergence time and lower power consumption. The results show that it effectively detects the R peaks in the extracted FECG with a sensitivity of 95.74-100% and a specificity of 100%. The parallel architecture shows up to an 85.88% reduction in the convergence time for non-invasive FECG databases while the series architecture shows a 27.41% reduction in the number of flip flops used when compared with the existing FPGA implementations of various FECG extraction methods. It also shows an increase of 2-7.51% in accuracy when compared to previous works.