A Fingertip-Mimicking 12×16 200µm-Resolution e-skin Taxel Readout Chip with per-Taxel Spiking Readout and Embedded Receptive Field Processing.

This paper presents an electronic skin (e-skin) taxel array readout chip in 0.18µm CMOS technology, achieving the highest reported spatial resolution of 200µm, comparable to human fingertips. A key innovation is the integration on chip of a 12×16 polyvinylidene fluoride (PVDF)-based piezoelectric sensor array with per-taxel signal conditioning frontend and spiking readout combined with local embedded neuromorphic first-order processing through Complex Receptive Fields (CRFs). Experimental results show that Spiking Neural Network (SNN)-based classification of the chip's spatiotemporal spiking output for input tactile stimuli such as texture and flutter frequency achieves excellent accuracies up to 97.1% and 99.2%, respectively. SNN-based classification of the indentation period applied to the on-chip PVDF sensors achieved 95.5% classification accuracy, despite using only a small 256-neuron SNN classifier, a low equivalent spike encoding resolution of 3-5 bits, and a sub-Nyquist 2.2kevent/s population spiking rate, a state-of-the-art power consumption of 12.33nW per-taxel, and 75µW-5mW for the entire chip is obtained. Finally, a comparison of the texture classification accuracies between two on-chip spike encoder outputs shows that the proposed neuromorphic level-crossing sampling (NLCS) architecture with a decaying threshold outperforms the conventional bipolar level-crossing sampling (LCS) architecture with fixed threshold.

Brain Feature Extraction With an Artifact-Tolerant Multiplexed Time-Encoding Neural Frontend for True Real-Time Closed-Loop Neuromodulation.

Closed-loop neuromodulation is emerging as a more effective and targeted solution for the treatment of neurological symptoms compared to traditional open-loop stimulation. The majority of the present designs lack the ability to continuously record brain activity during electrical stimulation; hence they cannot fully monitor the treatment's effectiveness. This is due to the large stimulation artifacts that can saturate the sensitive readout circuits. To overcome this challenge, this work presents a rapid-artifact-recovery time-multiplexed neural readout frontend in combination with backend linear interpolation to reconstruct the artifact-corrupted local field potentials' (LFP) features. Our hybrid technique is an alternative approach to avoid power-hungry large-dynamic-range readout architectures or large and complex artifact template subtraction circuits. We discuss the design and measurements of a prototype implementation of the proposed readout frontend in 180-nm CMOS. It combines time multiplexing and time-domain conversion in a novel 13-bit incremental ADC, requiring only 0.0018 mm2/channel of readout area despite the large 180-nm CMOS process used, while consuming only 4.51 µW/channel. This is the smallest reported area for stimulation-voltage-compatible technologies (i.e. ≥ 65 nm). The frontend also yields a best-in-class peak total harmonic distortion of -72.6 dB @2.5-mVpp input, thanks to its implicit DAC mismatch-error shaping property. We employ the chip to measure brain LFP signals corrupted with artifacts, then perform linear interpolation and feature extraction on the measured signals and evaluate the reconstruction quality, using a set of sixteen commonly used features and three stimulation scenarios. The results show relative accuracies above 95% with respect to the situation without artifacts. This work is an ideal candidate for integration in high-channel-count true closed-loop neuromodulation systems.

Improving the Accuracy of Spiking Neural Networks for Radar Gesture Recognition Through Preprocessing.

Event-based neural networks are currently being explored as efficient solutions for performing AI tasks at the extreme edge. To fully exploit their potential, event-based neural networks coupled to adequate preprocessing must be investigated. Within this context, we demonstrate a 4-b-weight spiking neural network (SNN) for radar gesture recognition, achieving a state-of-the-art 93% accuracy within only four processing time steps while using only one convolutional layer and two fully connected layers. This solution consumes very little energy and area if implemented in event-based hardware, which makes it suited for embedded extreme-edge applications. In addition, we demonstrate the importance of signal preprocessing for achieving this high recognition accuracy in SNNs compared to deep neural networks (DNNs) with the same network topology and training strategy. We show that efficient preprocessing prior to the neural network is drastically more important for SNNs compared to DNNs. We also demonstrate, for the first time, that the preprocessing parameters can affect SNNs and DNNs in antagonistic ways, prohibiting the generalization of conclusions drawn from DNN design to SNNs. We demonstrate our findings by comparing the gesture recognition accuracy achieved with our SNN to a DNN with the same architecture and similar training. Unlike previously proposed neural networks for radar processing, this work enables ultralow-power radar-based gesture recognition for extreme-edge devices.

Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications.

Energy-constrained biomedical recording systems need power-efficient data converters and good signal compression in order to meet the stringent power consumption requirements of many applications. In literature today, typically a SAR ADC in combination with digital compression is used. Recently, alternative event-driven sampling techniques have been proposed that incorporate compression in the ADC, such as level-crossing A/D conversion. This paper describes the power efficiency analysis of such level-crossing ADC (LCADC) and the traditional fixed-rate SAR ADC with simple compression. A model for the power consumption of the LCADC is derived, which is then compared to the power consumption of the SAR ADC with zero-order hold (ZOH) compression for multiple biosignals (ECG, EMG, EEG, and EAP). The LCADC is more power efficient than the SAR ADC up to a cross-over point in quantizer resolution (for example 8 bits for an EEG signal). This cross-over point decreases with the ratio of the maximum to average slope in the signal of the application. It also changes with the technology and design techniques used. The LCADC is thus suited for low to medium resolution applications. In addition, the event-driven operation of an LCADC results in fewer data to be transmitted in a system application. The event-driven LCADC without timer and with single-bit quantizer achieves a reduction in power consumption at system level of two orders of magnitude, an order of magnitude better than the SAR ADC with ZOH compression. At system level, the LCADC thus offers a big advantage over the SAR ADC.

An integrated multi-electrode-optrode array for in vitro optogenetics.

Modulation of a group of cells or tissue needs to be very precise in order to exercise effective control over the cell population under investigation. Optogenetic tools have already demonstrated to be of great value in the study of neuronal circuits and in neuromodulation. Ideally, they should permit very accurate resolution, preferably down to the single cell level. Further, to address a spatially distributed sample, independently addressable multiple optical outputs should be present. In current techniques, at least one of these requirements is not fulfilled. In addition to this, it is interesting to directly monitor feedback of the modulation by electrical registration of the activity of the stimulated cells. Here, we present the fabrication and characterization of a fully integrated silicon-based multi-electrode-optrode array (MEOA) for in vitro optogenetics. We demonstrate that this device allows for artifact-free electrical recording. Moreover, the MEOA was used to reliably elicit spiking activity from ChR2-transduced neurons. Thanks to the single cell resolution stimulation capability, we could determine spatial and temporal activation patterns and spike latencies of the neuronal network. This integrated approach to multi-site combined optical stimulation and electrical recording significantly advances today's tool set for neuroscientists in their search to unravel neuronal network dynamics.

Integral equations formulation of plasmonic transmission lines.

In this paper, a comprehensive integral equation formulation of plasmonic transmission lines is presented for the first time. Such lines are made up of a number of metallic strips with arbitrary shapes and dimensions immersed within a stack of planar dielectric or metallic layers. These lines support a number of propagating modes. Each mode has its own phase constant, attenuation constant, and field distribution. The presented integral equation formulation is solved using the Method of Moments (MoM). It provides all the propagation characteristics of the modes. The new formulation is applied to a number of plasmonic transmission lines, such as: single rectangular strip, horizontally coupled strips, vertically coupled strips, triangular strip, and circular strip. The numerical study is performed in the frequency (wavelength) range of 150-450 THz (0.66-2.0 µm). The results of the proposed technique are compared with those obtained using Lumerical mode solution, and CST. Very good agreement has been observed. The main advantage of the MoM is its intrinsic speed for this type of problem compared to general purpose solvers.

Carbon nanotube circuit integration up to sub-20 nm channel lengths.

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 µm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Mixed-signal template-based reduction scheme for stimulus artifact removal in electrical stimulation.

Simultaneous electrical stimulation and recording are used to gain insights into the function of neuronal circuitry. However, artifacts produced by the electrical stimulation pulses prevent the recording of neural responses during, and a short period after, the stimulation duration. In this work, we describe a mixed-signal recording topology with template subtraction for removing the artifact during the stimulation pulse. Emulated artifacts generated from a lumped electrical circuit model and experimental artifacts in cardiac cell cultures are used to evaluate the topology. The simulations show that delays between the emulated artifact and its estimated compensation template represent the largest error source of the analog template subtraction. The quantization error appears like random noise and determines the threshold level for the action potential detection. Simulations show that removal of the artifacts is possible, allowing the detection of action potentials during the stimulation pulsing period, even for high-amplitude saturating artifacts. Measurement results with artifacts elicited in cardiac cell cultures show feasible applications of this topology. The proposed topology therefore promisingly opens up a previously unavailable detection window for improving the analysis of the neuronal activity.

A third-order complementary metal-oxide-semiconductor sigma-delta modulator operating between 4.2 K and 300 K.

This paper presents a third-order switched-capacitor sigma-delta modulator implemented in a standard 0.35-µm CMOS process. It operates from 300 K down to 4.2 K, achieving 70.8 dB signal-to-noise-plus-distortion ratio (SNDR) in a signal bandwidth of 5 kHz with a sampling frequency of 500 kHz at 300 K. The modulator utilizes an operational transconductance amplifier in its loop filter, whose architecture has been optimized in order to eliminate the cryogenic anomalies below the freeze-out temperature. At 4.2 K, the modulator achieves 67.7 dB SNDR consuming 21.17 µA current from a 3.3 V supply.

Towards a noise prediction model for in vivo neural recording.

The signal-to-noise ratio of in vivo extracellular neural recordings with microelectrodes is influenced by many factors including the impedance of the electrode-tissue interface, the noise of the recording equipment and biological background noise from distant neurons. In this work we study the different noise sources affecting the quality of neural signals. We propose a simplified noise model as an analytical tool to predict the noise of an electrode given its geometrical dimensions and impedance characteristics. With this tool we are able to quantify different noise sources, which is important to determine realistic noise specifications for the design of electronic neural recording interfaces.

A multichannel integrated circuit for electrical recording of neural activity, with independent channel programmability.

Since a few decades, micro-fabricated neural probes are being used, together with microelectronic interfaces, to get more insight in the activity of neuronal networks. The need for higher temporal and spatial recording resolutions imposes new challenges on the design of integrated neural interfaces with respect to power consumption, data handling and versatility. In this paper, we present an integrated acquisition system for in vitro and in vivo recording of neural activity. The ASIC consists of 16 low-noise, fully-differential input channels with independent programmability of its amplification (from 100 to 6000 V/V) and filtering (1-6000 Hz range) capabilities. Each channel is AC-coupled and implements a fourth-order band-pass filter in order to steeply attenuate out-of-band noise and DC input offsets. The system achieves an input-referred noise density of 37 nV/√Hz, a NEF of 5.1, a CMRR > 60 dB, a THD < 1% and a sampling rate of 30 kS/s per channel, while consuming a maximum of 70 µA per channel from a single 3.3 V. The ASIC was implemented in a 0.35 µm CMOS technology and has a total area of 5.6 × 4.5 mm². The recording system was successfully validated in in vitro and in vivo experiments, achieving simultaneous multichannel recordings of cell activity with satisfactory signal-to-noise ratios.

Towards a closed-loop system for stimulation and recording: an in vitro approach with embryonic cardiomyocytes.

Closed loop systems, in which stimulation parameters are adjusted according to recorded signals would reduce the occurrence of side effects of stimulation and broaden current therapeutic options. As a step towards a closed-loop clinical system, we developed a single electrode stimulation / recording system for an in vitro microelectrode array. The system was used in vitro to simultaneously stimulate and record cardiac cells. Results indicated that stimulation artifacts depend on the distance between recording electrode and stimulating electrode and on the voltage amplitude. No artifact reduction algorithm was required for detecting cardiac action potentials 2ms after stimulation if the stimulation pulses were less than or equal to ± 1.5 V, and the distance from stimulation site was more than 200 µm. Cardiac signal propagation was also investigated with this system.

A cryogenic analog to digital converter operating from 300 K down to 4.4 K.

This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) implemented in a standard 0.35 microm complementary metal oxide semiconductor (CMOS) process. It operates from room temperature down to 4.4 K, achieving 10.47 effective number of bits (ENOB) at room temperature. At 4.4 K, the ADC achieves 8.53 ENOB at 50 kS/s sampling rate with a current consumption of 90 microA from a 3.3 V supply. The ADC utilizes an improved comparator architecture, which performs offset cancellation by using preamplifiers designed for cryogenic operation. The conventional offset cancellation algorithm is also modified in order to eliminate the effect of cryogenic anomalies below freeze-out temperature. The power efficiency is significantly improved compared to the state of the art semiconductor ADCs operating in the same temperature range.