Observation of coupled mechanical resonance modes within suspended 3D nanowire arrays.

Complex yet compact nanoscale mechanisms have largely been absent due to the rather limited availability of components and integration techniques. Especially missing have been efficient interconnects with adjustable characteristics. To address this issue, we report here, for the first time, the transduction of collective modes in vertically stacked arrays of silicon nanowires suspended between couplers. In addition to the ambitious miniaturization, this composite resonator enables the control of coupling strength through the lithographic definition of coupler stiffness. A direct link is thus established between coupling strength and spectral response for two array architectures with nominally identical resonators but different couplers. A series of unique observations emerged in this platform, such as the splitting of a single mode into two closely spaced modes which raises the possibility of tunable bandpass filters with enhanced spectrum characteristics. Finally, intermodal coupling strengths were measured providing strong evidence about the collective nature of these modes.

Real- and Q-space travelling: multi-dimensional distribution maps of crystal-lattice strain (∊044) and tilt of suspended monolithic silicon nanowire structures.

Silicon nanowire-based sensors find many applications in micro- and nano-electromechanical systems, thanks to their unique characteristics of flexibility and strength that emerge at the nanoscale. This work is the first study of this class of micro- and nano-fabricated silicon-based structures adopting the scanning X-ray diffraction microscopy technique for mapping the in-plane crystalline strain (∊044) and tilt of a device which includes pillars with suspended nanowires on a substrate. It is shown how the micro- and nanostructures of this new type of nanowire system are influenced by critical steps of the fabrication process, such as electron-beam lithography and deep reactive ion etching. X-ray analysis performed on the 044 reflection shows a very low level of lattice strain (<0.00025 Δd/d) but a significant degree of lattice tilt (up to 0.214°). This work imparts new insights into the crystal structure of micro- and nanomaterial-based sensors, and their relationship with critical steps of the fabrication process.

Neuromorphic computing with multi-memristive synapses.

Neuromorphic computing has emerged as a promising avenue towards building the next generation of intelligent computing systems. It has been proposed that memristive devices, which exhibit history-dependent conductivity modulation, could efficiently represent the synaptic weights in artificial neural networks. However, precise modulation of the device conductance over a wide dynamic range, necessary to maintain high network accuracy, is proving to be challenging. To address this, we present a multi-memristive synaptic architecture with an efficient global counter-based arbitration scheme. We focus on phase change memory devices, develop a comprehensive model and demonstrate via simulations the effectiveness of the concept for both spiking and non-spiking neural networks. Moreover, we present experimental results involving over a million phase change memory devices for unsupervised learning of temporal correlations using a spiking neural network. The work presents a significant step towards the realization of large-scale and energy-efficient neuromorphic computing systems.

Superplastic behavior of silica nanowires obtained by direct patterning of silsesquioxane-based precursors.

Silica nanowires spanning 10 µm-deep trenches are fabricated from different types of silsesquioxane-based precursors by direct e-beam patterning on silicon followed by release through deep reactive ion etching. Nanowire aspect ratios as large as 150 are achieved with a critical dimension of about 50 nm and nearly rectangular cross-sections. In situ bending tests are carried out inside a scanning electron microscope, where the etch depth of 10 [Formula: see text] provides sufficient space for deformation. Silica NWs are indeed observed to exhibit superplastic behavior without fracture with deflections reaching the full etch depth, about two orders of magnitude larger than the nanowire thickness. A large-deformation elastic bending model is utilized for predicting the deviation from the elastic behavior. The results of forty different tests indicate a critical stress level of 0.1-0.4 GPa for the onset of plasticity. The study hints at the possibility of fabricating silica nanowires in a monolithic fashion through direct e-beam patterning of silsesquioxane-based resins. The fabrication technology is compatible with semiconductor manufacturing and provides silica nanowires with a very good structural integrity.

Energy Harvesting in Microscale with Cavitating Flows.

Energy harvesting from thermal energy has been widely exploited to achieve energy savings and clean technologies. In this research, a new cost-effective and environment-friendly solution is proposed for the growing individual energy needs thanks to the energy application of cavitating flows. With the aid of cavitating jet flows from microchannel configurations of different sizes, it is shown that significant temperature rise (as high as 5.7 °C) can be obtained on the surface of the thin plate. The obtained heat energy could be integrated to a thermoelectric power generator, which can be used as a power resource for consumer devices, such as cell phones and laptops. To explore the difference in the temperature rise with different microtube diameters, namely, 152, 256, 504, and 762 µm, and also with different upstream pressures of 10, 20, 40, and 60 bar, the cavitation flow patterns are captured and analyzed using an advanced high-speed visualization system. The analysis of the captured data showed that different flow patterns exist for different diameters of the microtubes, including a pattern shift from micro- to macroscale, which accompanied the pattern of temporal results very well.

An Insect Eye Inspired Miniaturized Multi-Camera System for Endoscopic Imaging.

In this work, we present a miniaturized high definition vision system inspired by insect eyes, with a distributed illumination method, which can work in dark environments for proximity imaging applications such as endoscopy. Our approach is based on modeling biological systems with off-the-shelf miniaturized cameras combined with digital circuit design for real time image processing. We built a 5 mm radius hemispherical compound eye, imaging a 180°×180° degrees field of view while providing more than 1.1 megapixels (emulated ommatidias) as real-time video with an inter-ommatidial angle ∆ϕ = 0.5° at 18 mm radial distance. We made an FPGA implementation of the image processing system which is capable of generating 25 fps video with 1080 × 1080 pixel resolution at a 120 MHz processing clock frequency. When compared to similar size insect eye mimicking systems in literature, the system proposed in this paper features 1000 × resolution increase. To the best of our knowledge, this is the first time that a compound eye with built-in illumination idea is reported. We are offering our miniaturized imaging system for endoscopic applications like colonoscopy or laparoscopic surgery where there is a need for large field of view high definition imagery. For that purpose we tested our system inside a human colon model. We also present the resulting images and videos from the human colon model in this paper.

A deep etching mechanism for trench-bridging silicon nanowires.

Introducing a single silicon nanowire with a known orientation and dimensions to a specific layout location constitutes a major challenge. The challenge becomes even more formidable, if one chooses to realize the task in a monolithic fashion with an extreme topography, a characteristic of microsystems. The need for such a monolithic integration is fueled by the recent surge in the use of silicon nanowires as functional building blocks in various electromechanical and optoelectronic applications. This challenge is addressed in this work by introducing a top-down, silicon-on-insulator technology. The technology provides a pathway for obtaining well-controlled silicon nanowires along with the surrounding microscale features up to a three-order-of-magnitude scale difference. A two-step etching process is developed, where the first shallow etch defines a nanoscale protrusion on the wafer surface. After applying a conformal protection on the protrusion, a deep etch step is carried out forming the surrounding microscale features. A minimum nanowire cross-section of 35 nm by 168 nm is demonstrated in the presence of an etch depth of 10 µm. Nanowire cross-sectional features are characterized via transmission electron microscopy and linked to specific process steps. The technology allows control on all dimensional aspects along with the exact location and orientation of the silicon nanowire. The adoption of the technology in the fabrication of micro and nanosystems can potentially lead to a significant reduction in process complexity by facilitating direct access to the nanowire during surface processes such as contact formation and doping.

MoS2 transistors operating at gigahertz frequencies.

The presence of a direct band gap and an ultrathin form factor has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulfide (MoS2) being the most studied representative of this family of materials. While diverse electronic elements, logic circuits, and optoelectronic devices have been demonstrated using ultrathin MoS2, very little is known about their performance at high frequencies where commercial devices are expected to function. Here, we report on top-gated MoS2 transistors operating in the gigahertz range of frequencies. Our devices show cutoff frequencies reaching 6 GHz. The presence of a band gap also gives rise to current saturation, allowing power and voltage gain, all in the gigahertz range. This shows that MoS2 could be an interesting material for realizing high-speed amplifiers and logic circuits with device scaling expected to result in further improvement of performance. Our work represents the first step in the realization of high-frequency analog and digital circuits based on 2D semiconductors.

Memristive biosensors under varying humidity conditions.

We attempt to examine the potential of silicon nanowire memristors in the field of nanobiosensing. The memristive devices are crystalline Silicon (Si) Nanowires (NWs) with Nickel Silicide (NiSi) terminals. The nanowires are fabricated on a Silicon-on-Insulator (SOI) wafer by an Ebeam Lithography Technique (EBL) process that allows high resolution at the nanoscale. A Deep Reactive Ion Etching (DRIE) technique is used to define free-standing nanowires. The close alignment between Silicon (Si) and Nickel-Silicide (NiSi) terminals forms a Schottky-barrier at their junction. The memristive effect of the fabricated devices matches well with the memristor theory. An equivalent circuit reproducing the memristive effect in current-voltage (I-V) characteristics of our silicon nanowires is presented too. The memristive silicon nanowire devices are then functionalized with anti-human VEGF (Vascular Endothelial Growth Factor) antibody and I-V characteristics are examined for the nanowires prior to and after protein functionalization. The uptake of bio-molecules linked to the surface of the memristive NWs is confirmed by the increased voltage gap in the hysteresis curve. The effects of varying humidity conditions on the conductivity of bio-modified memristive silicon nanowires are deeply investigated.

A comparative study on fabrication techniques for on-chip microelectrodes.

This paper presents an experimental study on different microelectrode fabrication techniques, with particular focus on the robustness of the surface insulation towards typical working conditions required in lab-on-a-chip applications. Pt microelectrodes with diameters of 50 µm, 100 µm and 200 µm are patterned on a Si substrate with SiO(2) film. Sputtered SiO(2), low-pressure chemical vapor deposition (LPCVD) low-temperature oxide (LTO), Parylene C, SU-8, and dry-film were deposited and patterned on top of the chips as the passivation layer. This paper provides the detailed fabrication processes, the adhesion enhancement strategies, and the major advantages and disadvantages of each fabrication technique. Firstly, the quality and adhesion strength of the passivations were investigated by means of hydrolysis tests, in which sputtered SiO(2) and dry-film resist showed serious delamination issues and LTO showed minor defects. Secondly, the reliability of the microelectrodes was tested by impedance measurements after overnight ethanol incubation and self-assembled monolayer (SAM) formation. Thirty chips, representing a total of 300 electrodes, were measured, and statistical analyses of the results were conducted for each passivation technique. All of the electrodes passivated with these five techniques showed consistent impedance values after ethanol incubation. On the other hand, only LTO, Parylene C, and SU-8 ensured uniform electrical behavior after SAM formation. Having used both hydrolysis and impedance tests to verify the superior quality of the Parylene-based passivation, electrochemical experiments were performed to study the long-term stability of the passivation layer. Finally, the electrodes were incubated with electroactive alkanethiols functionalized with ferrocene. Square-wave voltammetry measurements demonstrated reproducible results on electrochemical label detection, which confirms the suitability of the Parylene passivation for charge-transfer-based measurements.

High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector.

This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle information is used to find the minimum energy operation point, corresponding maximum clock frequency, as well as the dissipated energy per clock cycle. The application of the model is demonstrated by exploring the energy efficiency of pipelining, retiming, and register balancing. Simulation results, which are obtained during a fraction of SPICE simulation time, are validated by measurements on a wavelet-based cardiac event detector that was fabricated in 65-nm low-leakage high-threshold technology. The mean of the absolute modeling error is calculated as 5.2%, with a standard deviation of 6.6% over the measurement points. The cardiac event detector dissipates 0.88 pJ/sample at a supply voltage of 320 mV.

Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization.

The design of a high-density neural recording system targeting epilepsy monitoring is presented. Circuit challenges and techniques are discussed to optimize the amplifier topology and the included OTA. A new platform supporting active recording devices targeting wireless and high-resolution focus localization in epilepsy diagnosis is also proposed. The post-layout simulation results of an amplifier dedicated to this application are presented. The amplifier is designed in a UMC 0.18µm CMOS technology, has an NEF of 2.19 and occupies a silicon area of 0.038 mm(2), while consuming 5.8 µW from a 1.8-V supply.

A cell-electrode interface noise model for high-density microelectrode arrays.

A cell-electrode interface noise model is developed which is dedicated to enable the co-simulation of the cell-electrode electrical characteristics, along with the electronics of novel CMOS-based MEA. The electrode noise is investigated for Pt and Pt black electrodes. It is shown that the electrode noise can be the dominant noise source in the full system. Moreover, Pt black electrodes benefit from up to 5 microV(rms) decrease of the electrode output noise, for small electrodes. Furthermore, the cell-electrode interface noise spectral density is shown to be 10 dB to 20 dB larger at 1 kHz when a cell is lying on top of the electrode. This increase depends on the neural cell adhesion on the MEA surface.

An electrical model of the cell-electrode interface for high-density microelectrode arrays.

A point-contact model is presented, and an area-contact model has been analytically derived in order to model the electrical characteristic of the cell-electrode interface of high-density neuron cultures. The area-contact model is presented as a model more suitable for subcellular multi-electrode resolution, which is a requisite for modeling and simulating the electrical behavior of novel high-density microelectrode arrays. Furthermore, when the electrode is aligned and centered with the cell, an optimum electrode diameter for recording the electrical activity of neural cells can be analytically derived, which is between 7-8 microm with a typical load capacitance of 10 pF.