CMOS-Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin.

The development of data-intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory-centric paradigm. Within this context, ternary content-addressable memory (TCAM) can become an essential platform for high-speed in-memory matching applications of large data vectors. Compared to traditional static random-access memory (SRAM) designs, TCAM technology using non-volatile resistive memories (RRAMs) in two-transistor-two-resistor (2T2R) configurations presents a cost-efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory-based TCAMs for large-scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive-bridge memories (CBRAMs) integrated with existing complementary metal-oxide-semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity-enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM-based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

Artificial Visual Systems Fabricated with Ferroelectric van der Waals Heterostructure for In-Memory Computing Applications.

Rapid developments in artificial neural network techniques and retina-inspired artificial visual systems are required to realize the sensing, processing, and memorization of an optical signal in a single device. Herein, a ferroelectric field-effect transistor fabricated with CuInP2S6 and α-In2Se3 van der Waals heterostructures is proposed and demonstrated for the development of an artificial visual system. The dipole polarizations are coupled and bidirectionally locked inside the ferroelectric α-In2Se3 along the in-plane and out-of-plane directions and are controlled by the gate voltages. Furthermore, light-induced polarization can change the order of polarization of the dipoles inside α-In2Se3. We demonstrate that using the combined control of these electrical and optical signals, the device may function like a retina-inspired vision system. The device can operate across a wide wavelength range (405-850 nm) and detect very low incident light (0.03 mW/cm2). Color recognition, high paired-pulse facilitation (∼170%), and short- to long-term memory transitions through quick learning are observed using this device. Additionally, this device demonstrates different complex processing abilities, including pattern recognition, light adaptation, optical logic operation, and event learning. The proposed ferroelectric heterostructure-based artificial visual system can serve as an essential bridge for fulfilling the future requirements of all-in-one sensing and memory-processing devices.

Dual Piezoelectric Energy Investing and Harvesting Interface for High-Voltage Input.

A novel harvesting interface for multiple piezoelectric transducers (PZTs) is proposed for high-voltage energy harvesting. Pre-biasing a PZT prior to its mechanical deformation increases its damping force, resulting in higher energy extraction. Unlike the conventional harvesters where a PZT-generated output is assumed to be continuous sinusoidal and output polarity is assumed to be alternating every cycle, PZT-generated output from human motion is expected to be random. Therefore, in the proposed approach, energy is invested to the PZT only when PZT deformation is detected. Upon the motion detection, energy stored at a storage capacitor (CSTOR) from earlier energy harvesting cycle is invested to pre-bias PZT, enhancing energy extraction. The harvested energy is transferred to back CSTOR for energy investment on the next cycle and then excess energy is transferred to the battery. In addition, partial electric charge extraction (PECE) is adapted to extract a partial amount of charges from the PZT every time its voltage approaches the process limit of 40 V. Simulations with 0.35 µm BCD process show 7.61× (with PECE only) and 8.38× (with PECE and energy investment) improvement compared to the conventional rectifier-based harvesting scheme Proposed harvesting interface successfully harvests energy from excitations with open-circuit voltages up to 100 V.

Biologically Plausible Artificial Synaptic Array: Replicating Ebbinghaus' Memory Curve with Selective Attention.

The nature of repetitive learning and oblivion of memory enables humans to effectively manage vast amounts of memory by prioritizing information for long-term storage. Inspired by the memorization process of the human brain, an artificial synaptic array is presented, which mimics the biological memorization process by replicating Ebbinghaus' forgetting curve. To construct the artificial synaptic array, signal-transmitting access transistors and artificial synaptic memory transistors are designed using indium-gallium-zinc-oxide and poly(3-hexylthiophene), respectively. To secure the desired performance of the access transistor in regulating the input signal to the synaptic transistor, the content of gallium in the access transistor is optimized. In addition, the operation voltage of the synaptic transistor is carefully selected to achieve memory-state efficiency. Repetitive learning characterizing Ebbinghaus' oblivion curves is realized using an artificial synaptic array with optimized conditions for both transistor components. This successfully demonstrates a biologically plausible memorization process. Furthermore, selective attention for information prioritization in the human brain is mimicked by selectively applying repetitive learning to a synaptic transistor with a high memory state. The demonstrated biologically plausible artificial synaptic array provides great scope for advancement in bioinspired electronics.

A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory.

For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (VTH) characteristic via the single negative differential resistance (NDR) phenomenon. In particular, recent advances in forming van der Waals (vdW) heterostructures with two-dimensional crystals have opened up new possibilities for realizing such NDR-based tunneling devices. However, it has been challenging to exhibit three VTH through the multiple-NDR (m-NDR) phenomenon in a single device even by using vdW heterostructures. Here, we show the m-NDR device formed on a BP/(ReS2 + HfS2) type-III double-heterostructure. This m-NDR device is then integrated with a vdW transistor to demonstrate a ternary vdW latch circuit capable of storing three logic states. Finally, the ternary latch is extended toward ternary SRAM, and its high-speed write and read operations are theoretically verified.

Functionalized Organic Material Platform for Realization of Ternary Logic Circuit.

Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required to achieve a stable MVL operation. In this study, an organic NDR (ONDR) device with double-peak transfer characteristics and a high peak-to-valley current ratio (PVCR; >102) is fabricated by utilizing an organic material platform for the development of a key element device for MVL applications. The organic NDT (ONDT) device is fabricated using a series connection of electron-dominant (P(NDI2OD-Se2)) and hole-dominant (P(DPP2DT-T2)) channel ambipolar organic field-effect transistors (AOFETs), and the NDR feature is achieved via correlated biasing of the ONDT device. The PVCR of the ONDT device can reach up to 13,000 via carrier transfer modulation of the AOFETs by varying the PMMA:P(VDF-TrFE) ratio of the mixed layer that is used as the top-gate dielectric of each AOFET. Further, ternary latch circuit operation is demonstrated using the developed ONDR device that stores three logic states with three distinct and controllable output states by adjusting the PMMA:P(VDF-TrFE) ratio of the dielectric layer.

A High-Voltage Energy-Harvesting Interface for Irregular Kinetic Energy Harvesting in IoT Systems with 1365% Improvement Using All-NMOS Power Switches and Ultra-low Quiescent Current Controller.

An energy-harvesting interface for kinetic energy harvesting from high-voltage piezoelectric and triboelectric generators is proposed in this paper. Unlike the conventional kinetic energy-harvesting interfaces optimized for continuous sinusoidal input, the proposed harvesting interface can efficiently handle irregular and random high voltage energy inputs. An N-type mosfet (NMOS)-only power stage design is introduced to simplify power switch drivers and minimize conduction loss. Controller active mode power is also reduced by introducing a new voltage peak detector. For efficient operation with potentially long intervals between random kinetic energy inputs, standby power consumption is minimized by monitoring the input with a 43 pW wake-up controller and power-gating all other circuits during the standby intervals. The proposed harvesting interface can harvest energy from a wide range of energy inputs, 10 s of nJ to 10 s of µJ energy/pulse, with an input voltage range of 5-200 V and an output range of 2.4-4 V under discontinuous as well as continuous excitation. The proposed interface is examined in two scenarios, with integrated power stage devices (maximum input 45 V) and with discrete power stage devices (maximum input 200 V), and the harvesting efficiency is improved by up to 600% and 1350%, respectively, compared to the case when harvesting is performed with a full bridge rectifier.

Remote Gating of Schottky Barrier for Transistors and Their Vertical Integration.

This paper introduces a strategy to modulate a Schottky barrier formed at a graphene-semiconductor heterojunction. The modulation is performed by controlling the work function of graphene from a gate that is placed laterally away from the graphene-semiconductor junction, which we refer to as the remote gating of a Schottky barrier. The remote gating relies on the sensitive work function of graphene, whose local variation induced by locally applied field effect affects the change in the work function of the entire material. Using Kelvin probe force microscopy analysis, we directly visualize how this local variation in the work function propagates through graphene. These properties of graphene are exploited to assemble remote-gated vertical Schottky barrier transistors (v-SBTs) in an unconventional device architecture. Furthermore, a vertical complementary circuit is fabricated by simply stacking two remote-gated v-SBTs (pentacene layer as the p-channel and indium gallium zinc oxide layer as the n-channel) vertically. We consider that the remote gating of graphene and the associated device architecture presented herein facilitate the extendibility of graphene-based v-SBTs in the vertical assembly of logic circuits.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

A 10.6mm3 Fully-Integrated, Wireless Sensor Node with 8GHz UWB Transmitter.

This paper presents a complete, autonomous, wireless temperature sensor, fully encapsulated in a 10.6mm3 volume. The sensor includes solar energy harvesting with an integrated 2 µAh battery, optical receiver for programming, microcontroller and memory, 8GHz UWB transmitter, and miniaturized custom antennas with a wireless range of 7 meters. Full, stand-alone operation was demonstrated for the first time for a system of this size and functionality.