Self-Assembled Photochromic Molecular Dipoles for High-Performance Polymer Thin-Film Transistors.

The development of high-performance multifunctional polymer-based electronic circuits is a major step toward future flexible electronics. Here, we demonstrate a tunable approach to fabricate such devices based on rationally designed dielectric super-lattice structures with photochromic azobenzene molecules. These nanodielectrics possessing ionic, molecular, and atomic polarization are utilized in polymer thin-film transistors (TFTs) to realize high-performance electronics with a p-type field-effect mobility (µFET) exceeding 2 cm2 V-1 s-1. A crossover in the transport mechanism from electrostatic dipolar disorder to ionic-induced disorder is observed in the transistor characteristics over a range of temperatures. The facile supramolecular design allows the possibility to optically control the extent of molecular and ionic polarization in the ultrathin nanodielectric. Thus, we demonstrate a 3-fold increase in the capacitance from 0.1 to 0.34 µF/cm2, which results in a 200% increase in TFT channel current.

Solution-Processed Carbon Nanotube True Random Number Generator.

With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is an increasing demand for robust security protocols when transmitting and receiving sensitive data. Toward this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudorandom number generators. However, the vast network of devices and sensors envisioned for the "Internet of Things" will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for next-generation security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Tunable Radiation Response in Hybrid Organic-Inorganic Gate Dielectrics for Low-Voltage Graphene Electronics.

Solution-processed semiconductor and dielectric materials are attractive for future lightweight, low-voltage, flexible electronics, but their response to ionizing radiation environments is not well understood. Here, we investigate the radiation response of graphene field-effect transistors employing multilayer, solution-processed zirconia self-assembled nanodielectrics (Zr-SANDs) with ZrOx as a control. Total ionizing dose (TID) testing is carried out in situ using a vacuum ultraviolet source to a total radiant exposure (RE) of 23.1 µJ/cm(2). The data reveal competing charge density accumulation within and between the individual dielectric layers. Additional measurements of a modified Zr-SAND show that varying individual layer thicknesses within the gate dielectric tuned the TID response. This study thus establishes that the radiation response of graphene electronics can be tailored to achieve a desired radiation sensitivity by incorporating hybrid organic-inorganic gate dielectrics.

Layer-by-Layer Assembled 2D Montmorillonite Dielectrics for Solution-Processed Electronics.

Layer-by-layer assembled 2D montmorillonite nanosheets are shown to be high-performance, solution-processed dielectrics. These scalable and spatially uniform sub-10 nm thick dielectrics yield high areal capacitances of ≈600 nF cm(-2) and low leakage currents down to 6 × 10(-9) A cm(-2) that enable low voltage operation of p-type semiconducting single-walled carbon nanotube and n-type indium gallium zinc oxide field-effect transistors.

Solution-Processed Self-Assembled Nanodielectrics on Template-Stripped Metal Substrates.

The coupling of hybrid organic-inorganic gate dielectrics with emergent unconventional semiconductors has yielded transistor devices exhibiting record-setting transport properties. However, extensive electronic transport measurements on these high-capacitance systems are often convoluted with the electronic response of the semiconducting silicon substrate. In this report, we demonstrate the growth of solution-processed zirconia self-assembled nanodielectrics (Zr-SAND) on template-stripped aluminum substrates. The resulting Zr-SAND on Al structures leverage the ultrasmooth (r.m.s. roughness <0.4 nm), chemically uniform nature of template-stripped metal substrates to demonstrate the same exceptional electronic uniformity (capacitance ∼700 nF cm(-2), leakage current <1 µA cm(-2) at -2 MV cm(-1)) and multilayer growth of Zr-SAND on Si, while exhibiting superior temperature and voltage capacitance responses. These results are important to conduct detailed transport measurements in emergent transistor technologies featuring SAND as well as for future applications in integrated circuits or flexible electronics.

Solution-processed carbon nanotube thin-film complementary static random access memory.

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control.

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Ambient-processable high capacitance hafnia-organic self-assembled nanodielectrics.

Ambient and solution-processable, low-leakage, high capacitance gate dielectrics are of great interest for advances in low-cost, flexible, thin-film transistor circuitry. Here we report a new hafnium oxide-organic self-assembled nanodielectric (Hf-SAND) material consisting of regular, alternating π-electron layers of 4-[[4-[bis(2-hydroxyethyl)amino]phenyl]diazenyl]-1-[4-(diethoxyphosphoryl) benzyl]pyridinium bromide) (PAE) and HfO2 nanolayers. These Hf-SAND multilayers are grown from solution in ambient with processing temperatures ≤150 °C and are characterized by AFM, XPS, X-ray reflectivity (2.3 nm repeat spacing), X-ray fluorescence, cross-sectional TEM, and capacitance measurements. The latter yield the largest capacitance to date (1.1 µF/cm(2)) for a solid-state solution-processed hybrid inorganic-organic gate dielectric, with effective oxide thickness values as low as 3.1 nm and have gate leakage <10(-7) A/cm(2) at ±2 MV/cm using photolithographically patterned contacts (0.04 mm(2)). The sizable Hf-SAND capacitances are attributed to relatively large PAE coverages on the HfO2 layers, confirmed by X-ray reflectivity and X-ray fluorescence. Random network semiconductor-enriched single-walled carbon nanotube transistors were used to test Hf-SAND utility in electronics and afforded record on-state transconductances (5.5 mS) at large on:off current ratios (I(ON):I(OFF)) of ~10(5) with steep 150 mV/dec subthreshold swings and intrinsic field-effect mobilities up to 137 cm(2)/(V s). Large-area devices (>0.2 mm(2)) on Hf-SAND (6.5 nm thick) achieve mA on currents at ultralow gate voltages (<1 V) with low gate leakage (<2 nA), highlighting the defect-free and conformal nature of this nanodielectric. High-temperature annealing in ambient (400 °C) has limited impact on Hf-SAND leakage densities (<10(-6) A/cm(2) at ±2 V) and enhances Hf-SAND multilayer capacitance densities to nearly 1 µF/cm(2), demonstrating excellent compatibility with device postprocessing methodologies. These results represent a significant advance in hybrid organic-inorganic dielectric materials and suggest synthetic routes to even higher capacitance materials useful for unconventional electronics.

Charge injection in high-κ gate dielectrics of single-walled carbon nanotube thin-film transistors.

We investigate charge injection into the gate dielectric of single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) having Al(2)O(3) and HfO(2) gate dielectrics. We demonstrate the use of electric field gradient microscopy (EFM) to identify the sign and approximate the magnitude of the injected charge carriers. Charge injection rates and saturation levels are found to differ between electrons and holes and also vary according to gate dielectric material. Electrically, Al(2)O(3) gated devices demonstrate smaller average hysteresis and notably higher average on-state current and p-type mobility than those gated by HfO(2). These differences in transfer characteristics are attributed to the charge injection, observed via EFM, and correlate well with differences in tunneling barrier height for electrons and holes formed in the conduction and valence at the SWCNT/dielectric interface, respectively. This work emphasizes the need to understand the SWCNT/dielectric interface to overcome charge injection that occurs in the focused field region adjacent to SWCNTs and indicates that large barrier heights are key to minimizing the effect.