ABSTRACT
In this work, we present a theoretical study on the use of Cu2ZnSn(S,Se)4 quantum wells in Cu2ZnSnS4 solar cells to enhance device efficiency. The role of different well thickness, number, and S/(S + Se) composition values is evaluated. The physical mechanisms governing the optoelectronic parameters are analyzed. The behavior of solar cells based on Cu2ZnSn(S,Se)4 without quantum wells is also considered for comparison. Cu2ZnSn(S,Se)4 quantum wells with a thickness lower than 50 nm present the formation of discretized eigenstates which play a fundamental role in absorption and recombination processes. Results show that well thickness plays a more important role than well number. We found that the use of wells with thicknesses higher than 20 nm allow for better efficiencies than those obtained for a device without nanostructures. A record efficiency of 37.5% is achieved when 36 wells with a width of 50 nm are used, considering an S/(S + Se) well compositional ratio of 0.25.
ABSTRACT
A numerical simulation is a valuable tool since it allows the optimization of both time and the cost of experimental processes for time optimization and the cost of experimental processes. In addition, it will enable the interpretation of developed measurements in complex structures, the design and optimization of solar cells, and the prediction of the optimal parameters that contribute to manufacturing a device with the best performance. In this sense, a detailed simulation study was carried out in this work by the Solar Cell Capacitance Simulator (SCAPS). In particular, we evaluate the influence of absorber and buffer thickness, absorber defect density, work function in back contact, Rs, Rsh, and carrier concentration on a CdTe/CdS cell to maximize its performance. Furthermore, the incorporation effect of ZnO:Al (TCO) and CuSCN (HTL) nanolayers was studied for the first time. As a result, the efficiency of the solar cell was maximized from 16.04% to 17.74% by increasing the Jsc and Voc. This work will play an essential role in enhancing the performance of CdTe-based devices with the best performance.
