ABSTRACT
With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.
ABSTRACT
Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al2O3, SiO2 equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage ( Vth) instability under negative gate bias stress at various measurement delays ( tm), stress biases ( VGSTR), temperatures ( T), and stress times ( tstr) for the first time. Thin top-gated oxide enables low VGSTR that is closer to the operating condition and ultrafast Vth measurements with low delay ( tm = 10 µs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of Vth degradation (Δ Vth) shows fast saturation at longer stress times and low-temperature activation energy. Vth instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different VGSTR and T. It is shown that measurements using larger tm show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying tm (1 ms being the lowest due to a low drain current level for thick oxide), VGSTR, and T to benchmark our top-gated results. Nonsaturating Δ Vth in the back-gated devices is shown to result from recovery artifacts due to the large tm (1 ms and greater) values. Finally, using a VGSTR and T-dependent first-order model, we show that the top-gated Al2O3 BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature.
