Achieving High-Performance Polymer-Wrapper-Free Aligned Carbon Nanotube Field-Effect Transistors Through Degradable Polymer Wrapping and Efficient Removal Techniques.

Semiconducting carbon nanotubes (s-CNTs) have emerged as a promising alternative to traditional silicon for ultrascaled field-effect transistors (FETs), owing to their exceptional properties. Aligned s-CNTs (A-CNTs) are particularly favored for practical applications due to their ability to provide higher driving current and lower contact resistance compared with individual s-CNTs or random networks. Achieving high-semiconducting-purity A-CNTs typically involves conjugated polymer wrapping for selective separation of s-CNTs, followed by self-assembly techniques. However, the presence of the polymer wrapper on A-CNTs can adversely impact electrical contact, gating efficiency, carrier transport, and device-to-device variations, necessitating its complete removal. While various methods have been explored for polymer removal, accurately characterizing the extent of removal remains a challenge. Traditional techniques such as absorption spectroscopy and X-ray photoelectron spectroscopy (XPS) may not accurately depict the remaining polymer content on A-CNTs due to their inherent detection limits. Consequently, the performance of FETs based on pure polymer-wrapper-free A-CNTs is unclear. In this study, we present an approach for preparing high-semiconducting-purity and polymer-wrapper-free A-CNTs using poly[(9,9-dioctylfluorenyl-2,7-dinitrilomethine)-(9,9-dioctylfluorenyl-2,7-dimethine)] (PFO-N-PFO), a degradable polymer, in conjunction with a modified dimension-limited self-alignment process (m-DLSA). Comprehensive transmission electron microscopy (TEM) characterizations, complemented by absorption and XPS characterizations, provide robust evidence of the successful near-complete removal of the polymer wrapper via a cleaning procedure involving acidic degradation, hot solvent rinsing, and vacuum annealing. Furthermore, top-gated FETs based on these high-semiconducting-purity and polymer-wrapper-free A-CNTs exhibit good performance metrics, including an on-current (Ion) of 2.2 mA/µm, peak transconductance (gm) of 1.1 mS/µm, low contact resistance (Rc) of 191 Ω·µm, and negligible hysteresis, representing a significant advancement in the CNT-based FET technology.

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/µm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors.

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35 mV dec-1 with a high on-state current of up to 4.9 µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

Aligned carbon nanotube-based electronics on glass wafer.

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by "head-to-head" comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)-based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a "90-nm" node silicon device, indicating a three- to four-generation superiority. Moreover, a record gate delay of 9.86 ps is achieved by our ring oscillator, which exceeds silicon even at a lower supply voltage. Furthermore, the fabrication of basic logic gates indicates the potential for further digital integrated circuits. All of these results highlight ACNT-based FETs on the glass wafer as an effective solution/platform for further development of CNT-based electronics.

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping.

Diodes based on p-n junctions are fundamental building blocks for numerous circuits, including rectifiers, photovoltaic cells, light-emitting diodes (LEDs), and photodetectors. However, conventional doping techniques to form p- or n-type semiconductors introduce impurities that lead to Coulomb scattering. When it comes to low-dimensional materials, controllable and stable doping is challenging due to the feature of atomic thickness. Here, by selectively depositing dielectric layers of Y2O3 and AlN, direct formation of wafer-scale carbon-nanotube (CNT) diodes are demonstrated with high yield and spatial controllability. It is found that the oxygen interstitials in Y2O3, and the oxygen vacancy together with Al-Al bond in AlN/Y2O3 electrostatically modulate the intrinsic CNTs channel, which leads to p- and n-type conductance, respectively. These CNTs diodes exhibit a high rectification ratio (>104) and gate-tunable rectification behavior. Based on these results, we demonstrate the applicability of the diodes in electrostatic discharge (ESD) protection and photodetection.

Improving Carbon Nanotube-Based Radiofrequency Field-Effect Transistors by the Device Architecture and Doping Process.

The semiconducting carbon nanotube (CNT) has been considered a promising candidate for future radiofrequency (RF) electronics due to its excellent electrical properties of high mobility and small capacitance. After decades of development, great progress has been achieved on CNT-based RF field-effect transistors (FETs). However, almost all elevations are owing to advancement of the CNT materials and fabrication process, while the study of device architecture is seldom considered and reported. In this work, we innovatively combined device architecture and related doping processes to further optimize CNT-based RF FETs by guiding process or materials with collaborative optimization for the first time and explore their effect on device performance carefully and statistically. Based on more mature random-oriented CNT materials, we fabricated CNT-based RF FETs having three different gate positions of device architecture variation accompanied by suitable doping schemes. The optimized FETs obtained 2-3 times of current density (transconductance) and 1.3 times the cutoff frequency and maximum oscillation frequency compared with unoptimized devices at the same channel length. After transistor-level verification of effect, we further built a CNT RF amplifier and demonstrated almost 10 dB of transducer gain improvement operating at 8 GHz for X-band application. The achieved results from this work would help further improve CNT RF performance beyond the materials and process point of view.

Unzipping Carbon Nanotubes to Sub-5-nm Graphene Nanoribbons on Cu(111) by Surface Catalysis.

Graphene nanoribbons (GNRs) are promising in nanoelectronics for their quasi-1D structures with tunable bandgaps. The methods for controllable fabrication of high-quality GNRs are still limited. Here a way to generate sub-5-nm GNRs by annealing single-walled carbon nanotubes (SWCNTs) on Cu(111) is demonstrated. The structural evolution process is characterized by low-temperature scanning tunneling microscopy. Substrate-dependent measurements on Au(111) and Ru(0001) reveal that the intermediate strong SWCNT-surface interaction plays a pivotal role in the formation of GNRs.