A 5.8 GHz 1.8 V +20 dBm 32.5% PAE Power Amplifier for a Short-Range Over-the-Air WPT Application.

This paper presents a 5.8 GHz differential cascode power amplifier for an over-the-air wireless power transfer application. Over-the-air wireless power transfer provides a variety of benefits in several applications such as the Internet of Things and medical implantation applications. The proposed PA features two fully differentially active stages with a custom-designed transformer to provide a single-ended output. The custom-made transformer shows a high quality factor, as high as 11.6 and 11.2 for the primary and secondary sides at 5.8 GHz. Fabricated using a standard 180 nm CMOS process, the amplifier achieves input and output matching of -14.7 dB and -29.7 dB, respectively. To achieve a high power level and efficiency, accurate optimization through power matching, Power Added Efficiency (PAE), and the design of the transformer are carried out while the supply voltage is limited to 1.8 V. Measurement results show a 20 dBm output power with a PAE as high as 32.5%, which makes the PA suitable for application, and it can be implanted while arrayed with various antenna arrays. Finally, a FOM is introduced to compare the performance of the work with similar works in the literature.

A High-Power 3P3T Cross Antenna Switch with Low Harmonic Distortion and Enhanced Isolation Using T-Type Pull-Down Path for Cellular Mobile Devices.

This paper presents a radio frequency (RF) triple pole triple throw 3P3T cross antenna switch for cellular mobile devices. The negative biasing scheme was applied to improve the power-handling capability and linearity of the switch by increasing the maximum tolerable voltage drop across the drain and source and reverse biasing the parasitic junction diodes. To avoid signal reflection through the antenna in off-state, all the antenna ports were equipped with 50-ohm termination to provide the pull-down path. Considering the simultaneous operation of antenna ports in different switch cases, the presented T-type pull-down path demonstrated improvement of isolation by over 15 dB. Using stacked switches, the 3P3T handled the input power level of over 35 dBm. The chip was manufactured in 65 nm complementary metal oxide semiconductor (CMOS) silicon on insulator (SOI) technology with a die size of 790 × 730 µm. The proposed structure achieved insertion loss, isolation, and voltage standing wave ratio (VSWR) of less than -0.9 dB, -40 dB, and 1.6, respectively, when the input signal was 3.8 GHz. The measured results prove the implemented switch shows the second and third harmonic distortion performances of less than -60 dBm when the input power level and frequency are 25 dBm and 3.8 GHz, respectively.

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of -10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and -11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is -11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT.

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.

A 0.617-2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode.

This paper presents a Dual-Port-15-Throw (DP15T) antenna switch module (ASM) Radio Frequency (RF) switch implemented by a branched antenna technique which has a high linearity for wireless communications and various frequency bands, including a low- frequency band of 617-960 MHz, a mid-frequency band of 1.4-2.2 GHz, and a high-frequency band of 2.3-2.7 GHz. To obtain an acceptable Insertion Loss (IL) and provide a consistent input for each throw, a branched antenna technique is proposed that distributes a unified magnetic field at the inputs of the throws. The other role of the proposed antenna is to increase the inductance effects for the closer ports to the antenna pad in order to decrease IL at higher frequencies. The module is enhanced by two termination modes for each antenna path to terminate the antenna when the switch is not operating. The module is fabricated in the silicon-on-insulator CMOS process. The measurement results show a maximum IMD2 and IMD3 of -100 dBm, while for the second and third harmonics the maximum value is -89 dBc. The module operates with a maximum power handling of 35 dBm. Experimental results show a maximum IL of 0.34 and 0.92 dB and a minimum isolation of 49 dB and 35.5 dB at 0.617 GHz and 2.7 GHz frequencies, respectively. The module is implemented in a compact way to occupy an area of 0.74 mm2. The termination modes show a second harmonic of 75 dBc, which is desirable.

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA.

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.