Honokiol inhibits epithelial-mesenchymal transition and hepatic fibrosis via activation of Ecadherin/GSK3ß/JNK and inhibition of AKT/ERK/p38/ß-catenin/TMPRSS4 signaling axis.

Though Honokiol was known to have anti-inflammatory, antioxidant, anticancer, antithrombotic, anti-viral, metabolic, antithrombotic, and neurotrophic activities, the underlying mechanisms of Honokiol on epithelial-mesenchymal transition (EMT) mediated liver fibrosis still remain elusive so far. Anti-EMT and antifibrotic effects of Honokiol were explored in murine AML-12 hepatocyte cells by 3-(4,5-dimethylthiazol-2-yl)-2,5-diphenyl-2H-tetrazolium bromide (MTT) assay, wound healing assay, Western blotting and also in CCl4-induced liver injury mouse model by immunohistochemistry. Honokiol significantly suppressed transforming growth factor ß1 (TGF-ß1)-induced EMT and migration of AML-12 cells along with decreased EMT phenotypes such as loss of cell adhesion and formation of fibroblast like mesenchymal cells in TGF-ß1-treated AML-12 cells. Consistently, Honokiol suppressed the expression of Snail and transmembrane protease serine 4 (TMPRSS4), but not p-Smad3, and activated E-cadherin in TGF-ß1-treated AML-12 cells. Additionally, Honokiol reduced the expression of ß-catenin, p-AKT, p-ERK, p-p38 and increased phosphorylation of glycogen synthase kinase 3 beta (GSK3ß) and JNK in TGF-ß1-treated AML-12 cells via TGF-ß1/nonSmad pathway. Conversely, GSK3ß inhibitor SB216763 reversed the ability of Honokiol to reduce Snail, ß-catenin and migration and activate E-cadherin in TGF-ß1-treated AML-12 cells. Also, Honokiol suppressed hepatic steatosis and necrosis by reducing the expression of TGF-ß1 and α-SMA in liver tissues of CCl4 treated mice. These findings provide scientific evidence that Honokiol suppresses EMT and hepatic fibrosis via activation of E-cadherin/GSK3ß/JNK and inhibition of AKT/ERK/p38/ß-catenin/TMPRSS4 signaling axis.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 µA/µm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator.

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO2/Si3N4 dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si3N4 single-layer insulator are conducted to the simulation works together. The stacked TiO2/Si3N4 GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO2/Si3N4 than that of a Si3N4 single-layer insulator. However, the electrical field and current density increased by the stacked TiO2/Si3N4 layers make the device's temperature higher. That results in the degradation of the device's performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO2/Si3N4-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; Ron increased from 1.41 mΩ·cm2 to 2.56 mΩ·cm2, and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO2/Si3N4-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si3N4 single-layer insulator.

Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time.

We present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a Si/SiGe heterojunction double-gate MOSFET. In the proposed 1T-DRAM, the program process is based on band-to-band tunneling (BTBT) between gate 1 and gate 2 regions, and a sensing margin is defined by the amount of excess holes stored in the SiGe body region. Therefore, the sensing margin and retention time were affected by SiGe in the body region. The BTBT rate, enhanced by the small band-gap energy in SiGe, increased the sensing margin. The Si/SiGe heterojunction between the source/drain and body regions formed a potential barrier for hole carriers. The retention time was improved by suppressing the diffusion of hole carriers in the floating-body storage node. In addition, the retention characteristic was also enhanced by applying a gate underlap structure, which significantly reduced the electric field-induced recombination rate. The optimized device with a Si0.7Ge0.3 body and underlap length (Lunderlap) of 5 nm exhibited a high sensing margin of 6.16 µA/µm and long retention time of 131 ms at a high temperature of 358 K.

Design Optimization and Analysis of InGaAs/InAs/InGaAs Heterojunction-Based Electron Hole Bilayer Tunneling FETs.

In this study, we have designed and analyzed the electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) based on various III-V compound semiconductor materials using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET has lower subthreshold swing (S) and higher on-state current (Ion) than the conventional planar TFET, using band-to-band tunneling (BTBT) across the source-to-channel junction. It uses a bias-induced BTBT across the EHB formed by an electric field between the two gates. The III-V compound semiconductors have been applied to the EHB TFETs to improve the switching performances and current drivability owing to their superior material properties such as high electron mobility and high tunneling probability. After the design and analysis of devices based on various compound semiconductors, in terms of primary DC characteristics, a lower bandgap material (InAs) has been inserted in the tunneling region of the In0.53Ga0.47As EHB TFET to enhance the tunneling rate. This paper proposes an EHB TFET that uses vertically stacked InGaAs/InAs/InGaAs layers. Moreover, the design optimization process has been performed via simulations. The simulation results of the proposed EHB TFET show remarkable performances with Ion of 739.6 µA/µm, S of 1.9 mV/dec, and threshold voltage (Vth) of 7 mV at VDS 0.5 V.

Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor.

In this work, an InGaAs/GaAsSb-based P-type gate-all-around (GAA) arch-shaped tunneling fieldeffect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. The device performance was investigated in views of the on-state current (Ion), subthreshold swing (SS), and Ion/Ioff ratio. For high current drivability, InGaAs/GaAsSb heterojunction is used to form the broken bandgap. Owing to the GAA arch-shaped structure of the TFET, the tunneling region between source and channel extended, thus Ion and SS are improved. However, it has some performance variations that are related with the height of the source region (Hsource), the epitaxially grown thickness of the channel (tepi), and the height of the drain region (Hdrain). Therefore, we performed a design optimization of the proposed device with the variables of Hsource, tepi, and Hdrain. The designed and optimized InGaAs/GaAsSb-based P-type GAA arch-shaped TFET demonstrated an Ion of 215 µA/µm SS of 18 mV/dec and Ion/Ioff of 1.64 × 1012.

Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor.

In this study, one-transistor dynamic random-access memory (1T-DRAM) based on a symmetric double-gate Si junctionless transistor is proposed using technology computer-aided design simulation. The proposed device uses double gates that play different roles in realizing 1T-DRAM operation. Gate 1 is used as a switching node, and Gate 2 is used as a storage node. By controlling the different two gate workfunctions, a potential barrier is adjusted to store hole effectively. The operation characteristics were investigated regarding four different memory operation states to write "1", write "0", read, and hold. Also, the effects of two different gate workfunctions on sensing margin and retention characteristics are closely investigated. Through a set of optimally set gate workfunctions, 33 µA/µm of sensing margin and 38 ms of retention time have been obtained.

Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET).

The Ge/GaAs-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) have been designed and optimized using technology computer-aided design (TCAD) simulations. In our previous work, the silicon-based A-TFET was designed and demonstrated. However, to progress the electrical characteristics of A-TFET, the III-V compound heterojunction structures which has enhanced electrical properties must be adopted. Thus, the germanium with gallium arsenide (Ge/GaAs) is considered as key materials of A-TFET. The proposed device has a Ge-based p-doped source, GaAs-based i-doped channel and GaAs-based n-doped drain. Due to the critical issues of device performances, the doping concentration of source and channel region (Dsource, Dchannel), height of source region (Hsource) and epitaxially grown thickness of channel (tepi) was selected as design optimization variables of Ge/GaAs-based GAA A-TFET. The DC characteristics such as on-state current (ion), off-state current (ioff), subthreshold-swing (S) were of extracted and analyzed. Finally, the proposed device has a gate length (LG) of 90 nm, Dsource 5 × 1019 cm-3, Dchannel of 1018 cm-3, tepi of 4 nm, Hsource of 90 nm, R of 10 nm and demonstrate an ion of 2 mA/µm, S of 12.9 mV/dec.

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations.

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 µA/µm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

Analyses on RF Performances of Silicon-Compatible InGaAs-Based Planar-Type and Fin-Type Junctionless Field-Effect Transistors.

The InO.53Ga0.47As-based planar-type junctionless fieled-effect transistor (JLFET) and fin-type FET (FinFET) have been designed and characterized by technology computer-aided design (TCAD) simulations. Because of their attractive material characteristics, the combination of In0.53Ga0.47As and InP has been adopted in some of the most recent semiconductor devices. In particular, the In0.53Ga0.47As-based transistor using an InP buffer is highly attractive due to its superior electrostatic performance which results from the by particular characteristics of the In0.53Ga0.47As material. In this paper, we focus on using small-signal RF modeling and Y-parameter extraction methods th extract various RF characteristics, such as gate capacitance, transconductance (gm), cut-off frequency (fT), and maximum oscillation frequency (fmax). The proposed InO.53Ga0.47As-based FinFET exhibits an on-state current (Ion) of 1030 µA/µm and an off-state current (Ioff) of 1.2 x 10(-13) A/µm with a threshold voltage (Vth) of 0.1 V, and a subthreshold swing (S) of 96 mV/dec. In addition, fT and fmax are determined to be 243 GHz and 1.6 THz, respectively.

Design and analysis of vertical-channel gallium nitride (GaN) junctionless nanowire transistors (JNT).

Vertical-channel gallium nitride (GaN) junctionless nanowire transistor (JNT) has been designed and characterized by technology computer-aided design (TCAD) simulations. Various characteristics such as wide bandgap, strong polariztion field, and high electron velocity make GaN one of the attractive materials in advanced electronics in recent times. Nanowire-structured GaN can be applicable to various transistors for enhanced electrical performances by its geometrical feature. In this paper, we analyze the direct-current (DC) characteristics depending on various channel doping concentrations (N(ch)) and nanowire radii (R(NW)). Furthermore, the radio-frequency (RF) characteristics under optimized conditions are extracted by small-signal equivalent circuit modeling. For the optimally designed vertical GaN JNT demonstrated on-state current (I(on)) of 345 µA/µm and off-state current (I(off)) of 3.7 x 10(-18) A/µm with a threshold voltage (V(t)) of 0.22 V, and subthreshold swing (S) of 68 mV/dec. Besides, f(T) and f(max) under different operating conditions (gate voltage, V(GS)) have been obtained.

Heteromaterial gate tunneling field-effect transistor for high-speed and radio-frequency applications.

We propose a tunneling field-effect transistor (TFET) with a heteromaterial (HM)-gate not only for low standby power (LSTP) applications, which TFETs are genuinely suitable for, but also for high-speed performance by properly adjusting intrinsic gate capacitance (C(gg)). As a result of simulations in this work, the HM-gate TFET showed better subthreshold characteristics (smaller S) at an appropriate threshold voltage (V(th)) for LSTP applications, enhancing tunneling probability by modulating the difference in the metal workfunction (φ(m)) between the source-side gate (S-gate) and the drain-side gate (D-gate). Further, the C(gg) of HM-gate TFET were extracted and compared against that of conventional TFETs having gates with various φ(m)'s. Since lower C(gg) can be formed by high φ(m) in the D-gate, the HM-gate TFET has an excellent cut-off frequency (f(T)) and intrinsic delay time (τ) associated with the C(gg). We confirmed that the HM-gate TFET proposed in this work achieves superb performance for LSTP applications as well as high-frequency operations.