Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits.

Large-area 2D-material-based devices may find applications as sensor or photonics devices or can be incorporated in the back end of line (BEOL) to provide additional functionality. The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D-based logic circuits, the status of developments, and the definition of the gaps to be bridged is provided. Today, typical test vehicles for 2D devices are single-sheet devices fully integrated in a lab environment, but transfer to a more scaled device in a fab environment has been demonstrated. This work reviews the status of the module development, including considerations for setting up fab-compatible process routes for single-sheet devices. While further development on key modules is still required, substantial progress is made for MX2 channel growth, high-k dielectric deposition, and contact engineering. Finally, the process requirements for building ultra-scaled stacked nanosheets are also reflected on.

Impact of device scaling on the electrical properties of MoS2 field-effect transistors.

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 µS/µm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

Layer-controlled epitaxy of 2D semiconductors: bridging nanoscale phenomena to wafer-scale uniformity.

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, 2D materials with a unique layered structure have attracted tremendous interest in recent years, mainly motivated by their ultra-thin body nature and unique optoelectronic and mechanical properties. The development of scalable synthesis techniques is obviously a fundamental step towards the development of a manufacturable technology. Metal-organic chemical vapor deposition has recently been used for the synthesis of large area TMDs, however, an important milestone still needs to be achieved: the ability to precisely control the number of layers and surface uniformity at the nano-to micro-length scale to obtain an atomically flat, self-passivated surface. In this work, we explore various fundamental aspects involved in the chemical vapor deposition process and we provide important insights on the layer-dependence of epitaxial MoS2 film's structural properties. Based on these observations, we propose an original method to achieve a layer-controlled epitaxy of wafer-scale TMDs.

From the metal to the channel: a study of carrier injection through the metal/2D MoS2 interface.

Despite the fact that two-dimensional MoS2 films continue to be of interest for novel device concepts and beyond silicon technologies, there is still a lack of understanding on the carrier injection at metal/MoS2 interface and effective mitigation of the contact resistance. In this work, we develop a semi-classical model to identify the main mechanisms and trajectories for carrier injection at MoS2 contacts. The proposed model successfully captures the experimentally observed contact behavior and the overall electrical behavior of MoS2 field effect transistors. Using this model, we evaluate the injection trajectories for different MoS2 thicknesses and bias conditions. We find for multilayer (>2) MoS2, the contribution of injection at the contact edge and injection under the contact increase with lateral and perpendicular fields, respectively. Furthermore, we identify that the carriers are predominantly injected at the edge of the contact metal for monolayer and bilayer MoS2. Following these insights, we have found that the transmission line model could significantly overestimate the transfer length and hence the contact resistivity for monolayer and bilayer MoS2. Finally, we evaluate different contact strategies to improve the contact resistance considering the limiting injection trajectory.

Polarity control in WSe2 double-gate transistors.

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-dimensional transition metal dichalcogenides, such as MoS2 and WSe2, have recently attracted considerable interest thanks to their electrical properties. Here, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer WSe2. We show how modulation of the Schottky barriers at drain and source by a separate gate, named program gate, can enable the selection of the carriers injected in the channel, and achieved controllable polarity behaviour with ON/OFF current ratios >10(6) for both electrons and holes conduction. Polarity-controlled WSe2 transistors enable the design of compact logic gates, leading to higher computational densities in 2D-flatronics.