A Power Adaptive, 1.22-pW/Hz, 10-MHz Read-Out Front-End for Bio-Impedance Measurement.

This paper presents a read-out front-end application-specific integrated circuit (ASIC) for the measurement of tissue impedances. The 10 mm2 2-channel front-end ASIC is fabricated in a 0.18 µm CMOS technology. The measurement results show that the proposed ASIC operates over a frequency range of 100 Hz up to 10 MHz. The ASIC has 1.22 pW/Hz power performance, with an SNR over 72 dB for frequencies ≤ 1 MHz, and over 65 dB SNR for frequencies ≥ 1 MHz. The total measured power consumption of the read-out front-end is shown to range from 2.1 to 21.7 mW depending on the input frequency. To achieve a wide dynamic range, the instrumentation amplifier has an adaptive gain control feature, and it employs programmable bias currents and reconfigurable structure to save power while processing low-frequency signals. A dual digital-to-analog converter (DAC) hybrid SAR analog-to-digital converter (ADC) is presented that reduces the power consumption of the ADC driver by sevenfold for frequencies between 4 kHz and 1 MHz.

Structured Design Methodology to Achieve a High SNR Electrical Impedance Tomography.

In this paper, we present a methodology for designing the main circuit building blocks of an electrical impedance tomography (EIT) system. In particular, we derive equations that map system-level EIT specifications to the performance requirements of each circuit block. We also review the circuit architectures that are best suited for meeting a given set of performance requirements. Our proposed design methodology is focused on maximizing the EIT system's signal-to-noise ratio while minimizing total power consumption.

A 10 MHz Read-Out Chain for Electrical Impedance Tomography.

This paper presents the design and implementation of a read-out chain for electrical impedance tomography (EIT) imaging. The EIT imaging approach can be incorporated to take spectral images of the tissue under study, offering an affordable, portable device for home health monitoring. A fast read-out channel covering a wide range of frequencies is a must for such applications. The proposed read-out channel comprising a programmable gain instrumentation amplifier, an analog-to-digital converter (ADC), and an ADC driver is designed and fabricated in a 0.18  m CMOS technology. The proposed read-out chain operates over the wide frequency range of 100 Hz to 10 MHz, with an average signal-to-noise ratio of more than 60 dB. The entire read-out channel consumes between 6.9 and 21.8 mW, depending on its frequency of operation.

Signal-to-Noise Ratio Analysis of a Phase-Sensitive Voltmeter for Electrical Impedance Tomography.

In this paper, thorough analysis along with mathematical derivations of the matched filter for a voltmeter used in electrical impedance tomography systems are presented. The effect of the random noise in the system prior to the matched filter, generated by other components, are considered. Employing the presented equations allow system/circuit designers to find the maximum tolerable noise prior to the matched filter that leads to the target signal-to-noise ratio (SNR) of the voltmeter, without having to over-design internal components. A practical model was developed that should fall within 2 dB and 5 dB of the median SNR measurements of signal amplitude and phase, respectively. In order to validate our claims, simulation and experimental measurements have been performed with an analog-to-digital converter (ADC) followed by a digital matched filter, while the noise of the whole system was modeled as the input referred at the ADC input. The input signal was contaminated by a known value of additive white Gaussian noise (AWGN) noise, and the noise level was swept from 3% to 75% of the least significant bit (LSB) of the ADC. Differences between experimental and both simulated and analytical SNR values were less than 0.59 and 0.35 dB for RMS values ≥ 20% of an LSB and less than 1.45 and 2.58 dB for RMS values < 20% of an LSB for the amplitude and phase, respectively. Overall, this study provides a practical model for circuit designers in EIT, and a more accurate error analysis that was previously missing in EIT literature.