An ultrafast bipolar flash memory for self-activated in-memory computing.

In-memory computing could enhance computing energy efficiency by directly implementing multiply accumulate (MAC) operations in a crossbar memory array with low energy consumption (around femtojoules for a single operation). However, a crossbar memory array cannot execute nonlinear activation; moreover, activation processes are power-intensive (around milliwatts), limiting the overall efficiency of in-memory computing. Here we develop an ultrafast bipolar flash memory to execute self-activated MAC operations. Based on atomically sharp van der Waals heterostructures, the basic flash cell has an ultrafast n/p program speed in the range of 20-30 ns and an endurance of 8 × 106 cycles. Utilizing sign matching between the input voltage signal and the storage charge type, our bipolar flash can realize a rectified linear unit activation function during the MAC process with a power consumption for each operation of just 30 nW (or 5 fJ of energy). Using a convolutional neural network, we find that the self-activated MAC method has a simulated accuracy of 97.23%, tested on the Modified National Institute of Standards and Technology dataset, which is close to the conventional method where the MAC and activation operations are separated.

An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions.

With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe2 transistor that has multiple logic functions (AND and XNOR) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits.

Ultrathin Multibridge Channel Transistor Enabled by van der Waals Assembly.

Multibridge channel field-effect transistors (MBCFETs) enable improved gate control and flow of a large drive current and they are regarded as promising candidates for next-generation transistor architecture. However, in achieving a larger drive current with a thinner channel, limitations arise from the decrease in mobility when the thickness of the Si nanosheet is less than 5 nm. In addition, an increase in the leakage current is unavoidable when a large number of channels are stacked. Here, a 2D ultrathin MBCFET is demonstrate, constructed based on 2 nm/2 nm MoS2 channels. The normalized drive current (23.11 µA*µm µm-1 ) in each level channel of this MBCFET exceeds that of the latest seven-level-stacked Si MBCFET, while the leakage current is only 0.4% of this value, with the subthreshold swing reaching 60 mV dec-1 and an on/off ratio reaching up to 4 × 108 at room temperature. Furthermore, the drive current of this 2D ultrathin MBCFET can be further increased by regulating the polarity of the operation voltage to reduce the injection barrier. The combination of 2D materials and an MBC structure has the potential for use in high-performance and low-power-consumption electronics.

A Steep-Slope MoS2/Graphene Dirac-Source Field-Effect Transistor with a Large Drive Current.

In the continuous transistor feature size scaling down, the scaling of the supply voltage is stagnant because of the subthreshold swing (SS) limit. A transistor with a new mechanism is needed to break through the thermionic limit of SS and hold the large drive current at the same time. Here, by adopting the recently proposed Dirac-source field-effect transistor (DSFET) technology, we experimentally demonstrate a MoS2/graphene (1.8 nm/0.3 nm) DSFET for the first time, and a steep SS of 37.9 mV/dec at room temperature with nearly free hysteresis is observed. Besides, by bringing in the structure of gate-all-around (GAA), the MoS2/graphene DSFET exhibits a steeper SS of 33.5 mV/dec and a 40% increased normalized drive current up to 52.7 µA·µm/µm (VDS = 1 V) with a current on/off ratio of 108, which shows potential for low-power and high-performance electronics applications.

[Surveillance of malaria in Huai'an District, Huai'an City, 2009-2013].

OBJECTIVE: To analyze the results of malaria surveillance in Huai' an District in the recent 5 years, so as to provide the evidences for the establishment of suitable control strategy in the district. METHODS: The febrile patients among permanent and floating populations in Huai'an District from 2009 to 2013 were examined by immunity and etiology methods and the mosquito vector in this district were investigated. Results In recent 5 years, a total of 48,203 person-times among permanent population were examined, and no positives ones were found, and totally 360 person-times among floating population were examined, and 53 cases of malaria were detected, including 2 vivax malaria cases, 48 falciparum malaria cases and 2 undifferentiated cases, and the positive rate of the floating population was 14.72%. All the cases were exported workers infected in Africa and Southeast Asia. A total of 1,048 Anopheles sinensis mosquitoes were captured in 2003, no other Anopheles mosquitoes were found. CONCLUSIONS: In recent 5 years, no local malaria cases have been found in Huai' an District, but the imported cases increase, and moreover, the mosquito vector and the transmission condition of malaria still exist.