Neuromorphic electro-stimulation based on atomically thin semiconductor for damage-free inflammation inhibition.

Inflammation, caused by accumulation of inflammatory cytokines from immunocytes, is prevalent in a variety of diseases. Electro-stimulation emerges as a promising candidate for inflammatory inhibition. Although electroacupuncture is free from surgical injury, it faces the challenges of imprecise pathways/current spikes, and insufficiently defined mechanisms, while non-optimal pathway or spike would require high current amplitude, which makes electro-stimulation usually accompanied by damage and complications. Here, we propose a neuromorphic electro-stimulation based on atomically thin semiconductor floating-gate memory interdigital circuit. Direct stimulation is achieved by wrapping sympathetic chain with flexible electrodes and floating-gate memory are programmable to fire bionic spikes, thus minimizing nerve damage. A substantial decrease (73.5%) in inflammatory cytokine IL-6 occurred, which also enabled better efficacy than commercial stimulator at record-low currents with damage-free to sympathetic neurons. Additionally, using transgenic mice, the anti-inflammation effect is determined by ß2 adrenergic signaling from myeloid cell lineage (monocytes/macrophages and granulocytes).

Asymmetric conducting route and potential redistribution determine the polarization-dependent conductivity in layered ferroelectrics.

Precise control of the conductivity of layered ferroelectric semiconductors is required to make these materials suitable for advanced transistor, memory and logic circuits. Although proof-of-principle devices based on layered ferroelectrics have been demonstrated, it remains unclear how the polarization inversion induces conductivity changes. Therefore, function design and performance optimization remain cumbersome. Here we combine ab initio calculations with transport experiments to unveil the mechanism underlying the polarization-dependent conductivity in ferroelectric channel field-effect transistors. We find that the built-in electric field gives rise to an asymmetric conducting route formed by the hidden Stark effect and competes with the potential redistribution caused by the external field of the gate. Furthermore, leveraging our mechanistic findings, we control the conductivity threshold in α-In2Se3 ferroelectric channel field-effect transistors. We demonstrate logic-in-memory functionality through the implementation of electrically self-switchable primary (AND, OR) and composite (XOR, NOR, NAND) logic gates. Our work provides mechanistic insights into conductivity modulation in a broad class of layered ferroelectrics, providing foundations for their application in logic and memory electronics.

Assessment of visual function in blind mice and monkeys with subretinally implanted nanowire arrays as artificial photoreceptors.

Retinal prostheses could restore image-forming vision in conditions of photoreceptor degeneration. However, contrast sensitivity and visual acuity are often insufficient. Here we report the performance, in mice and monkeys with induced photoreceptor degeneration, of subretinally implanted gold-nanoparticle-coated titania nanowire arrays providing a spatial resolution of 77.5 µm and a temporal resolution of 3.92 Hz in ex vivo retinas (as determined by patch-clamp recording of retinal ganglion cells). In blind mice, the arrays allowed for the detection of drifting gratings and flashing objects at light-intensity thresholds of 15.70-18.09 µW mm-2, and offered visual acuities of 0.3-0.4 cycles per degree, as determined by recordings of visually evoked potentials and optomotor-response tests. In monkeys, the arrays were stable for 54 weeks, allowed for the detection of a 10-µW mm-2 beam of light (0.5° in beam angle) in visually guided saccade experiments, and induced plastic changes in the primary visual cortex, as indicated by long-term in vivo calcium imaging. Nanomaterials as artificial photoreceptors may ameliorate visual deficits in patients with photoreceptor degeneration.

12-inch growth of uniform MoS2 monolayer for integrated circuit manufacture.

Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides, provide an opportunity for beyond-silicon exploration. However, the lab to fab transition of 2D semiconductors is still in its preliminary stages, and it has been challenging to meet manufacturing standards of stability and repeatability. Thus, there is a natural eagerness to grow wafer-level, high-quality films with industrially acceptable scale-cost-performance metrics. Here we report an improved chemical vapour deposition synthesis method in which the controlled release of precursors and substrates predeposited with amorphous Al2O3 ensure the uniform synthesis of monolayer MoS2 as large as 12 inches while also enabling fast and non-toxic growth to reduce manufacturing costs. Transistor arrays were fabricated to further confirm the high quality of the film and its integrated circuit application potential. This work achieves the co-optimization of scale-cost-performance metrics and lays the foundation for advancing the integration of 2D semiconductors in industry-standard pilot lines.

Hybrid neuromorphic hardware with sparing 2D synapse and CMOS neuron for character recognition.

Neuromorphic computing enables efficient processing of data-intensive tasks, but requires numerous artificial synapses and neurons for certain functions, which leads to bulky systems and energy challenges. Achieving functionality with fewer synapses and neurons will facilitate integration density and computility. Two-dimensional (2D) materials exhibit potential for artificial synapses, including diverse biomimetic plasticity and efficient computing. Considering the complexity of neuron circuits and the maturity of complementary metal-oxide-semiconductor (CMOS), hybrid integration is attractive. Here, we demonstrate a hybrid neuromorphic hardware with 2D MoS2 synaptic arrays and CMOS neural circuitry integrated on board. With the joint benefit of hybrid integration, frequency coding and feature extraction, a total cost of twelve MoS2 synapses, three CMOS neurons, combined with digital/analogue converter enables alphabetic and numeric recognition. MoS2 synapses exhibit progressively tunable weight plasticity, CMOS neurons integrate and fire frequency-encoded spikes to display the target characters. The synapse- and neuron-saving hybrid hardware exhibits a competitive accuracy of 98.8% and single recognition energy consumption of 11.4 µW. This work provides a viable solution for building neuromorphic hardware with high compactness and computility.

An Optoelectronic Synapse Based on Two-Dimensional Violet Phosphorus Heterostructure.

Neuromorphic computing can efficiently handle data-intensive tasks and address the redundant interaction required by von Neumann architectures. Synaptic devices are essential components for neuromorphic computation. 2D phosphorene, such as violet phosphorene, show great potential in optoelectronics due to their strong light-matter interactions, while current research is mainly focused on synthesis and characterization, its application in photoelectric devices is vacant. Here, the authors combined violet phosphorene and molybdenum disulfide to demonstrate an optoelectronic synapse with a light-to-dark ratio of 106 , benefiting from a significant threshold shift due to charge transfer and trapping in the heterostructure. Remarkable synaptic properties are demonstrated, including a dynamic range (DR) of > 60 dB, 128 (7-bit) distinguishable conductance states, electro-optical dependent plasticity, short-term paired-pulse facilitation, and long-term potentiation/depression. Thanks to the excellent DR and multi-states, high-precision image classification with accuracies of 95.23% and 79.65% is achieved for the MNIST and complex Fashion-MNIST datasets, which is close to the ideal device (95.47%, 79.95%). This work opens the way for the use of emerging phosphorene in optoelectronics and provides a new strategy for building synaptic devices for high-precision neuromorphic computing.

An ultrafast bipolar flash memory for self-activated in-memory computing.

In-memory computing could enhance computing energy efficiency by directly implementing multiply accumulate (MAC) operations in a crossbar memory array with low energy consumption (around femtojoules for a single operation). However, a crossbar memory array cannot execute nonlinear activation; moreover, activation processes are power-intensive (around milliwatts), limiting the overall efficiency of in-memory computing. Here we develop an ultrafast bipolar flash memory to execute self-activated MAC operations. Based on atomically sharp van der Waals heterostructures, the basic flash cell has an ultrafast n/p program speed in the range of 20-30 ns and an endurance of 8 × 106 cycles. Utilizing sign matching between the input voltage signal and the storage charge type, our bipolar flash can realize a rectified linear unit activation function during the MAC process with a power consumption for each operation of just 30 nW (or 5 fJ of energy). Using a convolutional neural network, we find that the self-activated MAC method has a simulated accuracy of 97.23%, tested on the Modified National Institute of Standards and Technology dataset, which is close to the conventional method where the MAC and activation operations are separated.

Two-dimensional devices and integration towards the silicon lines.

Despite technical efforts and upgrades, advances in complementary metal-oxide-semiconductor circuits have become unsustainable in the face of inherent silicon limits. New materials are being sought to compensate for silicon deficiencies, and two-dimensional materials are considered promising candidates due to their atomically thin structures and exotic physical properties. However, a potentially applicable method for incorporating two-dimensional materials into silicon platforms remains to be illustrated. Here we try to bridge two-dimensional materials and silicon technology, from integrated devices to monolithic 'on-silicon' (silicon as the substrate) and 'with-silicon' (silicon as a functional component) circuits, and discuss the corresponding requirements for material synthesis, device design and circuitry integration. Finally, we summarize the role played by two-dimensional materials in the silicon-dominated semiconductor industry and suggest the way forward, as well as the technologies that are expected to become mainstream in the near future.

The Road for 2D Semiconductors in the Silicon Age.

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.

All-in-one two-dimensional retinomorphic hardware device for motion detection and recognition.

With the advent of the Internet of Things era, the detection and recognition of moving objects is becoming increasingly important1. The current motion detection and recognition (MDR) technology based on the complementary metal oxide semiconductor (CMOS) image sensors (CIS) platform contains redundant sensing, transmission conversion, processing and memory modules, rendering the existing systems bulky and inefficient in comparison to the human retina. Until now, non-memory capable vision sensors have only been used for static targets, rather than MDR. Here, we present a retina-inspired two-dimensional (2D) heterostructure based retinomorphic hardware device with all-in-one perception, memory and computing capabilities for the detection and recognition of moving trolleys. The proposed 2D retinomorphic device senses an optical stimulus to generate progressively tuneable positive/negative photoresponses and memorizes it, combined with interframe differencing computations, to achieve 100% separation detection of moving trichromatic trolleys without ghosting. The detected motion images are fed into a conductance mapped neural network to achieve fast trolley recognition in as few as four training epochs at 10% noise level, outperforming previous results from similar customized datasets. The prototype demonstration of a 2D retinomorphic device with integrated perceptual memory and computation provides the possibility of building compact, efficient MDR hardware.

Ultrathin Multibridge Channel Transistor Enabled by van der Waals Assembly.

Multibridge channel field-effect transistors (MBCFETs) enable improved gate control and flow of a large drive current and they are regarded as promising candidates for next-generation transistor architecture. However, in achieving a larger drive current with a thinner channel, limitations arise from the decrease in mobility when the thickness of the Si nanosheet is less than 5 nm. In addition, an increase in the leakage current is unavoidable when a large number of channels are stacked. Here, a 2D ultrathin MBCFET is demonstrate, constructed based on 2 nm/2 nm MoS2 channels. The normalized drive current (23.11 µA*µm µm-1 ) in each level channel of this MBCFET exceeds that of the latest seven-level-stacked Si MBCFET, while the leakage current is only 0.4% of this value, with the subthreshold swing reaching 60 mV dec-1 and an on/off ratio reaching up to 4 × 108 at room temperature. Furthermore, the drive current of this 2D ultrathin MBCFET can be further increased by regulating the polarity of the operation voltage to reduce the injection barrier. The combination of 2D materials and an MBC structure has the potential for use in high-performance and low-power-consumption electronics.

Ultrafast non-volatile flash memory based on van der Waals heterostructures.

Flash memory has become a ubiquitous solid-state memory device widely used in portable digital devices, computers and enterprise applications. The development of the information age has demanded improvements in memory speed and retention performance. Here we demonstrate an ultrafast non-volatile flash memory based on MoS2/hBN/multilayer graphene van der Waals heterostructures, which achieves an ultrafast writing/erasing speed of 20 ns through two-triangle-barrier modified Fowler-Nordheim tunnelling. Using detailed theoretical analysis and experimental verification, we postulate that a suitable barrier height, gate coupling ratio and clean interface are the main reasons for the breakthrough writing/erasing speed of our flash memory devices. Because of its non-volatility this ultrafast flash memory could provide the foundation for the next generation of high-speed non-volatile memory.

Two-dimensional ferroelectric channel transistors integrating ultra-fast memory and neural computing.

With the advent of the big data era, applications are more data-centric and energy efficiency issues caused by frequent data interactions, due to the physical separation of memory and computing, will become increasingly severe. Emerging technologies have been proposed to perform analog computing with memory to address the dilemma. Ferroelectric memory has become a promising technology due to field-driven fast switching and non-destructive readout, but endurance and miniaturization are limited. Here, we demonstrate the α-In2Se3 ferroelectric semiconductor channel device that integrates non-volatile memory and neural computation functions. Remarkable performance includes ultra-fast write speed of 40 ns, improved endurance through the internal electric field, flexible adjustment of neural plasticity, ultra-low energy consumption of 234/40 fJ per event for excitation/inhibition, and thermally modulated 94.74% high-precision iris recognition classification simulation. This prototypical demonstration lays the foundation for an integrated memory computing system with high density and energy efficiency.

A Logic-Memory Transistor with the Integration of Visible Information Sensing-Memory-Processing.

To meet the demands of future intelligent application scenarios, the time-efficient information acquisition and energy-efficient data processing capabilities of terminal electronic systems are indispensable. However, in current commercial visual systems, the visible information is collected by image sensors, converted into digital format data, and transferred to memory units and processors for subsequent processing tasks. As a result, most of the time and energy are wasted in the data conversion and movement, which leads to large time latency and low energy efficiency. Here, based on 2D semiconductor WSe2, a logic-memory transistor that integrates visible information sensing-memory-processing capabilities is successfully demonstrated. Furthermore, based on 3 × 3 fabricated devices, an artificial visible information sensing-memory-processing system is proposed to perform image distinction tasks, in which the time latency and energy consumption caused by data conversion and movement can be avoided. On the other hand, the logic-memory transistor can also execute digital logic processing (logic) and logic results storage (memory) at the same time, such as AND logic function. Such a logic-memory transistor could provide a compact approach to develop next-generation efficient visual systems.

Two-dimensional materials for next-generation computing technologies.

Rapid digital technology advancement has resulted in a tremendous increase in computing tasks imposing stringent energy efficiency and area efficiency requirements on next-generation computing. To meet the growing data-driven demand, in-memory computing and transistor-based computing have emerged as potent technologies for the implementation of matrix and logic computing. However, to fulfil the future computing requirements new materials are urgently needed to complement the existing Si complementary metal-oxide-semiconductor technology and new technologies must be developed to enable further diversification of electronics and their applications. The abundance and rich variety of electronic properties of two-dimensional materials have endowed them with the potential to enhance computing energy efficiency while enabling continued device downscaling to a feature size below 5 nm. In this Review, from the perspective of matrix and logic computing, we discuss the opportunities, progress and challenges of integrating two-dimensional materials with in-memory computing and transistor-based computing technologies.

A MoS2 /PTCDA Hybrid Heterojunction Synapse with Efficient Photoelectric Dual Modulation and Versatility.

Just as biological synapses provide basic functions for the nervous system, artificial synaptic devices serve as the fundamental building blocks of neuromorphic networks; thus, developing novel artificial synapses is essential for neuromorphic computing. By exploiting the band alignment between 2D inorganic and organic semiconductors, the first multi-functional synaptic transistor based on a molybdenum disulfide (MoS2 )/perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA) hybrid heterojunction, with remarkable short-term plasticity (STP) and long-term plasticity (LTP), is reported. Owing to the elaborate design of the energy band structure, both robust electrical and optical modulation are achieved through carriers transfer at the interface of the heterostructure, which is still a challenging task to this day. In electrical modulation, synaptic inhibition and excitation can be achieved simultaneously in the same device by gate voltage tuning. Notably, a minimum inhibition of 3% and maximum facilitation of 500% can be obtained by increasing the electrical number, and the response to different frequency signals indicates a dynamic filtering characteristic. It exhibits flexible tunability of both STP and LTP and synaptic weight changes of up to 60, far superior to previous work in optical modulation. The fully 2D MoS2 /PTCDA hybrid heterojunction artificial synapse opens up a whole new path for the urgent need for neuromorphic computation devices.

A non-volatile AND gate based on Al2O3/HfO2/Al2O3 charge-trap stack for in-situ storage applications.

The emergence of two-dimensional (2D) materials has inspired academia in microelectronics to find a novel device structure to offer a potential technological route for increasing energy efficiency and processing speed for data storage and computing at transistor level. Devices based on 2D materials include logic gates and memories, each with their own unique features. However, integrating logic function and memory into a single device has barely been studied. Here, we report a non-volatile AND gate based on Al2O3/HfO2/Al2O3 charge-trap stack. The device can store charges after completing logic operation. The ratio of high and low current states during logic operations can exceed 105. The output current states during the logic and memory operations still have a two orders of magnitude distinction after 800 s, indicating that this device possesses the non-volatile characteristic. The device has potential applications for in-situ memory applications, which makes it a possible candidate to break the "memory wall" at transistor level.

Two-dimensional materials for synaptic electronics and neuromorphic systems.

Synapses in biology provide a variety of functions for the neural system. Artificial synaptic electronics that mimic the biological neuron functions are basic building blocks and developing novel artificial synapses is essential for neuromorphic computation. Inspired by the unique features of biological synapses that the basic connection components of the nervous system and the parallelism, low power consumption, fault tolerance, self-learning and robustness of biological neural systems, artificial synaptic electronics and neuromorphic systems have the potential to overcome the traditional von Neumann bottleneck and create a new paradigm for dealing with complex problems such as pattern recognition, image classification, decision making and associative learning. Nowadays, two-dimensional (2D) materials have drawn great attention in simulating synaptic dynamic plasticity and neuromorphic computing with their unique properties. Here we describe the basic concepts of bio-synaptic plasticity and learning, the 2D materials library and its preparation. We review recent advances in synaptic electronics and artificial neuromorphic systems based on 2D materials and provide our perspective in utilizing 2D materials to implement synaptic electronics and neuromorphic systems in hardware.

A Photoelectric-Stimulated MoS2 Transistor for Neuromorphic Engineering.

The von Neumann bottleneck has spawned the rapid expansion of neuromorphic engineering and brain-like networks. Synapses serve as bridges for information transmission and connection in the biological nervous system. The direct implementation of neural networks may depend on novel materials and devices that mimic natural neuronal and synaptic behavior. By exploiting the interfacial effects between MoS2 and AlOx, we demonstrate that an h-BN-encapsulated MoS2 artificial synapse transistor can mimic the basic synaptic behaviors, including EPSC, PPF, LTP, and LTD. Efficient optoelectronic spikes enable simulation of synaptic gain, frequency, and weight plasticity. The Pavlov classical conditioning experiment was successfully simulated by electrical tuning, showing associated learning behavior. In addition, h-BN encapsulation effectively improves the environmental time stability of our devices. Our h-BN-encapsulated MoS2 artificial synapse provides a new paradigm for hardware implementation of neuromorphic engineering.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (ß âˆ¼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.