A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA.

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter-amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta-sigma modulator was designed and fabricated in a 0.18 µm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

In-Sensor Computing Realization Using Fully CMOS-Compatible TiN/HfOx-Based Neuristor Array.

With the evolution of artificial intelligence, the explosive growth of data from sensory terminals gives rise to severe energy-efficiency bottleneck issues due to cumbersome data interactions among sensory, memory, and computing modules. Heterogeneous integration methods such as chiplet technology can significantly reduce unnecessary data movement; however, they fail to address the fundamental issue of the substantial time and energy overheads resulting from the physical separation of computing and sensory components. Brain-inspired in-sensor neuromorphic computing (ISNC) has plenty of room for such data-intensive applications. However, one key obstacle in developing ISNC systems is the lack of compatibility between material systems and manufacturing processes deployed in sensors and computing units. This study successfully addresses this challenge by implementing fully CMOS-compatible TiN/HfOx-based neuristor array. The developed ISNC system demonstrates several advantageous features, including multilevel analogue modulation, minimal dispersion, and no significant degradation in conductance (@125 °C). These characteristics enable stable and reproducible neuromorphic computing. Additionally, the device exhibits modulatable sensory and multi-store memory processes. Furthermore, the system achieves information recognition with a high accuracy rate of 93%, along with frequency selectivity and notable activity-dependent plasticity. This work provides a promising route to affordable and highly efficient sensory neuromorphic systems.

A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of ±0.11 (3σ).

This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of ±0.11 °C (3σ), exceeding the accuracy of ±0.23 °C (3σ) achieved without calibration. We implement the sensor in a 0.18 µm CMOS process, occupying an area of 0.42 mm2. It achieves a resolution of 0.01 °C and has a conversion time of 24 ms.

Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform.

A broadband and CMOS-compatible polarization beam splitter and rotator (PSR) built on the silicon nitride-on-silicon multilayer platform is presented. The PSR is realized by cascading a polarization beam splitter and a polarization rotator, which are both subtly constructed with an asymmetrical directional coupler waveguide structure. The advantage of this device is that the function of PSR can be directly realized in the SiN layer, providing a promising solution to the polarization diversity schemes in SiN photonic circuits. The chip is expected to have high power handling capability as the light is input from the SiN waveguide. The use of silicon dioxide as the upper cladding of the device ensures its compatibility with the metal back-end-of-line process. By optimizing the structure parameters, a polarization conversion loss lower than 1 dB and cross talk larger than 27.6 dB can be obtained for TM-TE mode conversion over a wavelength range of 1450 to 1600 nm. For TE mode, the insertion loss is lower than 0.26 dB and cross talk is larger than 25.3 dB over the same wavelength range. The proposed device has good potential in diversifying the functionalities of the multilayer photonic chip with high integration density.

CMOS-compatible, broadband, and polarization-independent edge coupler for efficient chip coupling with standard single-mode fiber.

A CMOS-compatible, broadband, and polarization-independent edge coupler for efficient chip coupling with standard single-mode fiber is proposed. Three layers of a silicon nitride waveguide array with the same structures are used in the top oxide cladding of the chip to achieve high coupling efficiency and to simplify the mode transformation structure. Optimal total coupling loss at the wavelength of 1550 nm, -0.49dB for TE mode polarization and -0.92dB for TM mode polarization is obtained. The -1dB bandwidth is beyond 160 nm for TE mode polarization and ∼130nm for TM mode polarization, respectively. A significant reduction in the packaging cost of silicon photonic chips is anticipated. Meanwhile, the structure holds vast potential for on-chip three-dimensional photonic integrations or fiber-to-chip, chip-to-chip optical interconnections.

Analysis of Orthogonal Coupling Structure Based on Double Three-Contact Vertical Hall Device.

A vertical Hall device is an important component of 3D Hall sensors, used for detecting magnetic fields parallel to the sensor surface. The Hall devices described in existing research still have problems, such as large offset voltage and low sensitivity. Aiming to solve these problems, this study proposes a double three-contact vertical Hall device with low offset voltage, and a conformal mapping analysis method to improve the sensitivity of the device. Secondly, an orthogonal coupling structure composed of two sets of double three-contact vertical Hall devices is proposed, which further reduces the offset voltage of the device. Finally, the TCAD simulation software was used to analyze the performance of the devices, and an existing vertical Hall device was compared to ours. The results show that the orthogonal coupling structure in this study exhibits better performance, reaching an average voltage sensitivity of 17.5222 mV/VT and an average offset voltage of about 0.075 mV. In addition, the structure has the same magnitude of offset voltage in the four phases of the rotating current method. This characteristic enables the back-end circuit to more accurately filter out the offset voltage and acquire the Hall signal.

A Large Measurable Range Capacitance-to-Digital Converter for Smart Humidity Sensors.

This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0-388 pF. The proposed CDC was realized using 0.18 µm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 µA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%-90% RH.

A Low Power Energy-Efficient Precision CMOS Temperature Sensor †.

This paper presents a low power, energy-efficient precision CMOS temperature sensor. The front-end circuit is based on bipolar junction transistors, and employs a pre-bias circuit and bipolar core. To reduce measurement errors arising from current ratio mismatch, a new dynamic element-matching mode is proposed, which dynamically matches all current sources in the front-end circuit. The first-order fitting and third-order fitting are used to calibrate the output results. On the basis of simulation results, the sensor achieves 3σ-inaccuracies of +0.18/-0.13 °C from -55 °C to +125 °C. Measurement results demonstrate sensor 3σ-inaccuracies of ±0.2 °C from 0 °C to +100 °C. The circuit is implemented in 0.18 µm CMOS, and consumes 6.1 µA with a 1.8 V supply voltage.