Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control". A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an "exposed top" structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates.

A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs) is presented for the first time, aiming at a 3 nm technology node and beyond. The nVSAFETs were fabricated by an integration flow of Si/SiGe epitaxy, quasi-atomic layer etching (qALE) of SiGe selective to Si, formation of SiGe/Si core/shell NS/NW structure, building of nitride dummy gate, and replacement of the dummy gate. This fabrication method is complementary metal oxide semiconductor (CMOS)-compatible, simple, and reproducible, and NWs with a diameter of 17 nm and NSs with a thickness of 20 nm were obtained. Excellent control of short-channel-effects was presented. The device performance was also investigated and discussed. The proposed integration scheme has great potential for applications in chip manufacturing, especially with vertical channel devices.