Topological photonic crystal nanowire array laser with bulk states.

A topological photonic crystal InGaAsP/InP core-shell nanowire array laser with bulk states operating in the 1550 nm band is proposed and simulated. By optimizing the structure parameters, high Q factor of 1.2 × 105 and side-mode suppression ratio of 13.2 dB are obtained, which are 28.6 and 4.6 times that of a uniform nanowire array, respectively. The threshold and maximum output are 17% lower and 613% higher than that of the uniform nanowire array laser, respectively, due to the narrower nanowire slits and stronger optical confinement. In addition, a low beam divergence angle of 2° is obtained due to the topological protection. This work may pave the way for the development of high-output, low-threshold, low-beam-divergence nanolasers.

Effective surface passivation of GaAs nanowire photodetectors by a thin ZnO capping.

The III-V nanowire (NW) structure is a good candidate for developing photodetectors. However, high-density surface states caused by the large surface-to-volume ratio severely limit their performance, which is difficult to solve in conventional ways. Here, a robust surface passivation method, using a thin layer of ZnO capping, is developed for promoting NW photodetector performance. 11 cycles of ZnO, grown on pure zinc blende high-quality GaAs NWs by atomic layer deposition, significantly alleviates the undesirable effect of the surface states, without noticeable degradation in NW morphology. An average 20-fold increase in micro-photoluminescence intensity is observed for passivated NWs, which leads to the development of detectors with high responsivity, specific detectivity, and optical gain of 9.46 × 105 A W-1, 3.93 × 1014 Jones, and 2.2 × 108 %, respectively, under low-intensity 532 nm illumination. Passivated NW detectors outperform their counterparts treated by conventional methods, so far as we know, which shows the potential and effectiveness of thin ZnO surface passivation on NW devices.

Initialization of Nanowire or Cluster Growth Critically Controlled by the Effective V/III Ratio at the Early Nucleation Stage.

For self-catalyzed nanowires (NWs), reports on how the catalytic droplet initiates successful NW growth are still lacking, making it difficult to control the yield and often accompanying a high density of clusters. Here, we have performed a systematic study on this issue, which reveals that the effective V/III ratio at the initial growth stage is a critical factor that governs the NW growth yield. To initiate NW growth, the ratio should be high enough to allow the nucleation to extend to the entire contact area between the droplet and substrate, which can elevate the droplet off of the substrate, but it should not be too high in order to keep the droplet. This study also reveals that the cluster growth between NWs is also initiated from large droplets. This study provides a new angle from the growth condition to explain the cluster formation mechanism, which can guide high-yield NW growth.

Non-〈111〉-oriented semiconductor nanowires: growth, properties, and applications.

In recent years, non-〈111〉-oriented semiconductor nanowires have attracted increasing interest in terms of fundamental research and promising applications due to their outstanding crystal quality and distinctive physical properties. Here, a comprehensive overview of recent advances in the study of non-〈111〉-oriented semiconductor nanowires is presented. We start by introducing various growth techniques for obtaining nanowires with certain orientations, for which the growth energetics and kinetics are discussed. Attention is then given to the physical properties of non-〈111〉 nanowires, as predicted by theoretical calculations or demonstrated experimentally. After that, we review the advantages and challenges of non-〈111〉 nanowires as building blocks for electronic and optoelectronic devices. Finally, we discuss the possible challenges and opportunities in the research field of non-〈111〉 semiconductor nanowires.

Low-Consumption Synaptic Devices Based on Gate-All-Around InAs Nanowire Field-Effect Transistors.

In this work, an artificial electronic synaptic device based on gate-all-around InAs nanowire field-effect transistor is proposed and analyzed. The deposited oxide layer (In2O3) on the InAs nanowire surface serves as a charge trapping layer for information storage. The gate voltage pulse serves as stimuli of the presynaptic membrane, and the drain current and channel conductance are treated as post-synaptic current and weights of the postsynaptic membrane, respectively. At low gate voltages, the device simulates synaptic behaviors including short-term depression and long-term depression. By increasing the amplitude and quantity of gate voltage pulses, the transition from short-term depression to long-term potentiation can be achieved. The device exhibits a large memory window of over 1 V and a minimal energy consumption of 12.5 pJ per synaptic event. This work may pave the way for the development of miniaturized low-consumption synaptic devices and related neuromorphic systems.