RESUMEN
Despite high demand for gold film nanostructuring, patterning gold at the nanoscale still presents considerable challenges for current foundry-compatible processes. Here, we present a method based on abrasive-free chemical mechanical planarization (CMP) to planarize nanostructured gold surfaces with high selectivity against SiO2. The method is efficient in a damascene process and industry-compatible. Investigations into the material removal mechanism explore the effects of CMP parameters and show that the material removal rate is highly tunable with changes in slurry composition. Millimeter-scale arrays of gold nanostructures embedded in SiO2 were fabricated and the planarization dynamics were monitored over time, leading to the identification of distinct planarization phases and their correlation with the material removal mechanism. Finally, plasmonic cavities of gold nanostructure arrays over a gold mirror were fabricated. The cavities exhibited efficient plasmonic resonance in the visible range, aligning well with simulation results.
RESUMEN
This paper presents a method to locally fine tune silicon-on-insulator (SOI) device layer thickness for the fabrication of optimal silicon photonics devices. Very precise control of thickness can be achieved with a modified local oxidation of silicon (LOCOS) process. The fabrication process is robust, complementary metal-oxide-semiconductor (CMOS) compatible and has the advantage of creating vertical tapers (~5.3 µm long for ~210 nm of height) required for impedance matching between sections of different height. The technology is demonstrated by fabricating a TE-pass filter.
RESUMEN
A major issue in the fabrication of integrated Bragg grating filters in highly confined waveguides is the average effective index fluctuations caused by waveguide dimension variations. Lateral variations are caused by the sidewall roughness created during the etching process while vertical variations are coming from the wafer silicon layer thickness non-uniformity. Grating spectral distortions are known to result solely from the low spatial frequency components of these variations. As a result, in this work, we present an experimental method to quantify such relevant spatial components by stitching a hundred high-resolution scanning electron microscope images. Additionally, we propose two techniques to reduce, in the design, the phase noise impact on integrated Bragg gratings without relying on fabrication process improvements. More specifically, we show that the use of hybrid multimode/singlemode waveguides reduce by more than one order of magnitude the effect of sidewall roughness on integrated Bragg gratings while we show that the fabrication of ultra-compact gratings in spiral waveguides mitigate the impact of the silicon layer thickness variations.
RESUMEN
We report on the design, fabrication, and demonstration of waveguide coupled channel drop filters at 1550 nm, on a silicon-on-insulator (SOI) substrate. These devices rely on resonant power transfer from a bus waveguide to side-walled Bragg resonators with quarter-wave shifts in the middle. By employing a second mirror resonator, and a tap-off waveguide, reflections along the bus waveguide can be reduced, leading to realization of circulator-free resonance filters. These devices were fabricated on SOI using e-beam lithography and inductively coupled plasma (ICP) etching. Fabricated devices with two coupled cavities are demonstrated to have rejection ratios greater than 20 dB and 3-dB bandwidths of 110 GHz, close to the values predicted by numerical modeling. We also demonstrate power tap-off at resonance of around 16 dB.