Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines.

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.

Sub-Nanosecond Switching of Si:HfO2 Ferroelectric Field-Effect Transistor.

The discovery of ferroelectric doped HfO2 enabled the emergence of scalable and CMOS-compatible ferroelectric field-effect transistor (FeFET) technology which has the potential to meet the growing need for fast, low-power, low-cost, and high-density nonvolatile memory, and neuromorphic devices. Although HfO2 FeFETs have been widely studied in the past few years, their fundamental switching speed is yet to be explored. Importantly, the shortest polarization time demonstrated to date in HfO2-based FeFET was ∼10 ns. Here, we report that a single subnanosecond pulse can fully switch HfO2-based FeFET. We also study the polarization switching kinetics across 11 orders of magnitude in time (300 ps to 8 s) and find a remarkably steep time-voltage relation, which is captured by the classical nucleation theory across this wide range of pulse widths. These results demonstrate the high-speed capabilities of FeFETs and help better understand their fundamental polarization switching speed limits and switching kinetics.

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications.

This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach of interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO2) and silicon oxynitride (SiON) as IL were fabricated and characterized. Although the FeFETs with SiO2 interfaces demonstrated better low-frequency characteristics compared to the FeFETs with SiON interfaces, the latter demonstrated better WRITE endurance and retention. Finally, the neuromorphic simulation was conducted to evaluate the performance of FeFETs with SiO2 and SiON IL as synaptic devices. We observed that the WRITE endurance in both types of FeFETs was insufficient to carry out online neural network training. Therefore, we consider an inference-only operation with offline neural network training. The system-level simulation reveals that the impact of systematic degradation via retention degradation is much more significant for inference-only operation than low-frequency noise. The neural network with FeFETs based on SiON IL in the synaptic core shows 96% accuracy for the inference operation on the handwritten digit from the Modified National Institute of Standards and Technology (MNIST) data set in the presence of flicker noise and retention degradation, which is only a 2.5% deviation from the software baseline.

Hardware functional obfuscation with ferroelectric active interconnects.

Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

Ferroelectric transistors with asymmetric double gate for memory window exceeding 12 V and disturb-free read.

Ferroelectric field-effect transistors (FeFETs) with a single gate structure and using the newly discovered ferroelectric hafnium oxide as an active material are attracting considerable interest for nonvolatile memory devices. However, such FeFETs struggle to achieve a large separation between the two logic states (memory window, MW) because of the thickness limitations of the ferroelectric film. Moreover, they are affected by detrimental disturbs coming from the read operation because of the shared write and read paths. Therefore, significant performance improvements are needed for the device to compete with established memory technologies like flash. Here, we present an asymmetric double-gate FeFET structure, where only one gate stack comprises the ferroelectric layer. We propose a novel read operation at the non-ferroelectric gate and demonstrate an amplified MW exceeding 12 V thanks to the enhanced body effect factor and the increased sensitivity of the transfer characteristics to the ferroelectric polarization. As a result, the above physical limitation is circumvented, thus by far outperforming the MW values reported in the literature. Based on this, we implement the multi-level cell storage featuring 4 bits per cell and stable data retention. Finally, an essential benefit originating from the separated write and read paths in our structure is exploited to demonstrate the fully disturb-free read operation. Besides memory, this could be particularly favorable for those neuromorphic and in-memory computing concepts with an occasional update of the stored variable but a very frequent read.

Ferroelectric field-effect transistors based on HfO2: a review.

In this article, we review the recent progress of ferroelectric field-effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2), ten years after the first report on such a device. With a focus on the use of FeFET for nonvolatile memory application, we discuss its basic operation principles, switching mechanisms, device types, material properties and array structures. Key device performance metrics such as cycling endurance, retention, memory window, multi-level operation and scaling capability are analyzed. We also briefly survey recent developments in alternative applications for FeFETs including neuromorphic and in-memory computing as well as radiofrequency devices.

Frequency Mixing with HfO2-Based Ferroelectric Transistors.

Second harmonic generation (SHG) and frequency mixing of electrical signals are fundamental for a wide range of radiofrequency applications. Recently, ferroelectric field-effect transistors (FeFETs), made from ferroelectric hafnium oxide (HfO2), have demonstrated promising SHG capabilities because of their unique symmetric transfer curves. In this paper, we illustrate how this symmetry is highly sensitive to material properties by varying the thickness of the ferroelectric layer and the doping of the silicon substrate. We show that the SHG conversion gain and the spectral purity are greatly increased (up to 96%) by precisely tuning the ferroelectric polarization reversal and the quantum tunneling currents. Based on this, we propose and experimentally demonstrate the generation of the difference and of the sum of two input frequencies (frequency mixing) with a single FeFET, which we attribute to the inherently strong quadratic component of the symmetric transfer characteristics. Because of the reversible and continuous ferroelectric switching in HfO2, our approach allows for an electrical control of the energy distribution of spectral components, thus opening up new and very promising paths for frequency manipulations with simple ferroelectric devices.

Structural and Electrical Comparison of Si and Zr Doped Hafnium Oxide Thin Films and Integrated FeFETs Utilizing Transmission Kikuchi Diffraction.

The microstructure of ferroelectric hafnium oxide plays a vital role for its application, e.g., non-volatile memories. In this study, transmission Kikuchi diffraction and scanning transmission electron microscopy STEM techniques are used to compare the crystallographic phase and orientation of Si and Zr doped HfO2 thin films as well as integrated in a 22 nm fully-depleted silicon-on-insulator (FDSOI) ferroelectric field effect transistor (FeFET). Both HfO2 films showed a predominately orthorhombic phase in accordance with electrical measurements and X-ray diffraction XRD data. Furthermore, a stronger texture is found for the microstructure of the Si doped HfO2 (HSO) thin film, which is attributed to stress conditions inside the film stack during crystallization. For the HSO thin film fabricated in a metal-oxide-semiconductor (MOS) like structure, a different microstructure, with no apparent texture as well as a different fraction of orthorhombic phase is observed. The 22 nm FDSOI FeFET showed an orthorhombic phase for the HSO layer, as well as an out-of-plane texture of the [111]-axis, which is preferable for the application as non-volatile memory.