Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features.

Exploitation of the oxidation behaviour in an environmentally sensitive semiconductor is significant to modulate its electronic properties and develop unique applications. Here, we demonstrate a native oxidation-inspired InSe field-effect transistor as an artificial synapse in device level that benefits from the boosted charge trapping under ambient conditions. A thin InOx layer is confirmed under the InSe channel, which can serve as an effective charge trapping layer for information storage. The dynamic characteristic measurement is further performed to reveal the corresponding uniform charge trapping and releasing process, which coincides with its surface-effect-governed carrier fluctuations. As a result, the oxide-decorated InSe device exhibits nonvolatile memory characteristics with flexible programming/erasing operations. Furthermore, an InSe-based artificial synapse is implemented to emulate the essential synaptic functions. The pattern recognition capability of the designed artificial neural network is believed to provide an excellent paradigm for ultra-sensitive van der Waals materials to develop electric-modulated neuromorphic computation architectures.

Probing Charge Transport Difference in Parallel and Vertical Layered Electronics with Thin Graphite Source/Drain Contacts.

In the present study, we aim to help improve the design of van der Waals stacking, i.e., vertical 2D electronics, by probing charge transport differences in both parallel and vertical conducting channels of layered molybdenum disulfide (MoS2), with thin graphite acting as source and drain electrodes. To avoid systematic errors and variable contact contributions to the MoS2 channel, parallel and vertical electronics are all fabricated and measured on the same conducting material. Large differences in the on/off current ratio, mobility, and charge fluctuations, between parallel and vertical electronics are evident in electrical performance as well as in charge transport mechanisms. Further insights are drawn from a well-constrained analysis of both temperature-dependent current-voltage characteristics and low-frequency (LF) current fluctuations. This work offers significant insight into the fundamental understanding of charge transport and the development of future layered-materials-based integration technology.

High Mobilities in Layered InSe Transistors with Indium-Encapsulation-Induced Surface Charge Doping.

Tunability and stability in the electrical properties of 2D semiconductors pave the way for their practical applications in logic devices. A robust layered indium selenide (InSe) field-effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The optimized InSe FETs deliver an unprecedented high electron mobility up to 3700 cm2 V-1 s-1 at room temperature, which can be retained with 60% after 1 month. Further insight into the evolution of the position of the Fermi level and the microscopic device structure with different In thicknesses demonstrates an enhanced electron-doping behavior at the In/InSe interface. Furthermore, the contact resistance is also improved through the In insertion between InSe and Au electrodes, which coincides with the analysis of the low-frequency noise. The carrier fluctuation is attributed to the dominance of the phonon scattering events, which agrees with the observation of the temperature-dependent mobility. Finally, the flexible functionalities of the logic-circuit applications, for instance, inverter and not-and (NAND)/not-or (NOR) gates, are determined with these surface-doping InSe FETs, which establish a paradigm for 2D-based materials to overcome the bottleneck in the development of electronic devices.